Comments Locked

38 Comments

Back to Article

  • GeoffreyA - Wednesday, February 16, 2022 - link

    Terrific stuff, Ian, and delightful reading! Thanks! Curiously, the many FOUPs in one picture reminded me of the final Citadel sequence in Half-Life 2, where aliens were strapped up in things very like that. And from your short description (would that it were longer!), I imagine the inside of an EUV machine looks a bit like something from another world or the future.
  • edzieba - Wednesday, February 16, 2022 - link

    Clearly the double-facemasks are not for contamination control reasons, but to dissuade from consuming the delicious fresh wafers.
  • PhantomTaco - Wednesday, February 16, 2022 - link

    That two meter wide half dome sounds to me like the Source Vessel. If it was the part of the tool that you've taken photos of without the skin, then it's definitely the Source
  • eastcoast_pete - Wednesday, February 16, 2022 - link

    Thanks Ian, would love to see more articles like this! Regarding the EUV Scanners: If those machines were indeed ASML EUV scanners (no one else sells EUV scanners right now), they might have been NXE:3600Ds; that's the most advanced one ASML currently sells, it's for 5 and 3 nm volume production. The reason I am guessing that's what they are is the height ratio of the panels; the 3600 has taller panels on the bottom, the 3400's (7 and 5 nm) panels are about equal in height. But again, just guessing based on your picture; I know you had to sign an NDA before they let you visit.
    So, if they really have a bunch of 3600s there, it'll get interesting...
  • PhantomTaco - Wednesday, February 16, 2022 - link

    Where do you get the panel sizing differences from?
  • eastcoast_pete - Thursday, February 17, 2022 - link

    ASML website. They show the two scanners. The 3600 has higher bottom panels on one side, the top and bottom panels on the 3400 are pretty much the same height.
  • Arsenica - Thursday, February 17, 2022 - link

    Im pretty sure the 3400C and 3600D look the same on the outside. The 3300B also had the same 2 tall side panels on the end where the EUV source goes but it also had a RV-like pattern instead of being all-white.

    The 3100's sides had 3 tall side panels because of its older EUV source design.
  • Papaspud - Wednesday, February 16, 2022 - link

    Nice catch!
  • Blastdoor - Wednesday, February 16, 2022 - link

    So this article got me thinking... Intel has had a bunch of EUV machines sitting around for several years not being used to make chips. The natural question -- what have they been using them for?

    Obvious answer -- they're trying to open up a portal into either (1) a parallel universe or (2) the past or future. Will demons start coming out of Intel fabs? Will a robot be sent back in time to kill Jim Keller before ehe designs Zen? Only time will tell...
  • Arsenica - Thursday, February 17, 2022 - link

    Intel has had development EUV tools working non stop since the late 2000's (first their Micro Exposure tool and then ASML pre-production machines), but they haven't been able to use them for shipping products for a variety of reasons so all they have been doing is running pre-qualification wafers.
  • dwillmore - Wednesday, February 16, 2022 - link

    Grammar error: " or if one brakes down," Breaks is the correct word. I guess one could break down by braking down, but that's probably not what you meant.
  • Mike Bruzzone - Wednesday, February 16, 2022 - link

    mb
  • prophet001 - Wednesday, February 16, 2022 - link

    Super cool write-up. Thanks!
  • thestryker - Wednesday, February 16, 2022 - link

    Love the fab trips even if they aren't able to give you any specifics as it's super interesting stuff that we rarely get a glimpse into.

    EUV + 8p0e would hint at perhaps Meteor Lake since I believe those are not only the first on an EUV node, but also using the tile packaging.
  • MananDedhia - Wednesday, February 16, 2022 - link

    Brings back memories of when I worked in GF Fab 8. Thank you for the article.
  • Drkrieger01 - Wednesday, February 16, 2022 - link

    This is why I read this website:
    "If anyone from TSMC is reading this, and we get traveling again, I’d love to get the opportunity to connect in person to do something for the technical community."

    It's these ideas to connect with big silicon companies, showing us what all is inside and exciting new generations to leap into the silicon field. I wish I had seen stuff like this when I was going through school, it would have cemented my path into computer engineering :)
  • fmcjw - Thursday, February 17, 2022 - link

    CDC is talking about opening up borders for business travel in 2H22 to Taiwan, and a site visit will be one of the best "applications" of that policy. Wish you success.
  • DanNeely - Thursday, February 17, 2022 - link

    Ian's in the UK, so it'd need to be their govt moving not the USA's. Oh and Taiwan's of course. From the twitter sidebar yesterday they still have a really long quarantine on arrival period that's prohibitive for most travelers.
  • CajunArson - Wednesday, February 16, 2022 - link

    "For those of you who read AnandTech often, you’ll know that I like die area calculations with simple wafer images – from the back-of-the-brain mathematics I was able to deduce we were looking at a leading edge wafer with ~400mm2 die area. I'll leave you to imagine what that might be."

    Sapphire Rapids tiles.
  • watersb - Wednesday, February 16, 2022 - link

    Wow!
  • psyopper - Wednesday, February 16, 2022 - link

    Thank you for writing this up and sharing it with others. As an Intel employee who works in D1 daily, I always enjoy reading the press tours to remind me just how fascinating it is to show up to work every day; it's easy to lose sight of that sense of awe when you've gone through the gowning process and are walking your way up and down that 1/2 mile long path for the fourth time today.

    I remember doing the same as you when I first started, doing die size calculations on the back of my hand to suss out what my tool was currently processing. Here's a fun trick: Excluding binning and assuming each die is 100% usable ... How many die were on the wafer? How many wafers were in the FOUP? What is the street price per processor? How much is that single FOUP worth in revenue to Intel? How many more of those FOUP's did you see flying around overhead or in process on tools?

    The reality is that the processors are all made similarly regardless of the actual product name or how the wafer gets cut up at the end of the line. The masks will change on the litho tool, but the chemistry used to create a transistor or metal interconnect is essentially the same if it's Meteor Lake or Granite Rapids. For us, it's not about the processor, but about the process itself.

    Funny side story about D1X - When you visit Ronler Acres you will see a number of fabs with extra large letters on the side: D1B, D1C, D1D and D1X. The local legend says that D1X was originally going to be named D1E but focus group input said it was too ominus to write what could be easily confused as DIE in 20 foot letters on the side of the largest building in Oregon, and since the letter X was all the rage in the 2000's, they used that instead. I have no idea if true, but funny to tell at least.
  • Ian Cutress - Wednesday, February 16, 2022 - link

    If you saw a madman with a security entourage being chased away from an EUV machine on the 10th of December, that was me! Follow my twitter, there may be some more related content coming.

    $ per FOUP is always a fun calculation.
  • psyopper - Thursday, February 17, 2022 - link

    For those not willing or able, the math usually comes out to around $1-2 million USD per FOUP at the end of the processing line. I don't know what Intel pays per wafer from the Si manufacturer, but $1000 feels like a good guess, so the FOUP is worth $25,000 at the beginning of the line, the price of a small car.
  • JKflipflop98 - Wednesday, February 16, 2022 - link

    . . . and since we don't have anyone with a sense of humor around, they chose to put a giant "DIX" on the side of the building instead.
  • psyopper - Thursday, February 17, 2022 - link

    Fort Dix, New Jersey has entered the chat...
  • Spunjji - Thursday, February 24, 2022 - link

    DIX Enormous
  • ballsystemlord - Wednesday, February 16, 2022 - link

    @Ian , I'd like to know, How'd they keep the wafers separate from the air? I'd imagine each pod is hermetically sealed, but what type of seal do they use?
    "It’s important to note that the wafers aren’t meant to be exposed to the air at all."
  • Wereweeb - Thursday, February 17, 2022 - link

    They use baby seals. Every year, Intel sacrifices millions of baby seals to their synthetic overlords, so that they are allowed to use the machines that imbues sand with the thinky-think. That's the true price for your 12900K.
  • ilt24 - Thursday, February 17, 2022 - link

    I think as a FOUP is sealed they pump nitrogen in, so when it is in transport or storage the wafers sit in N2. When a tool opens a FOUP, the wafer are exposed to whatever atmosphere exists in the tool, which could be the clear room air.
  • Eskimo - Thursday, February 17, 2022 - link

    Every company makes their own decisions based on the process and product requirements as well as experience and testing data. The state of the FOUPs can vary at various points in the production line. There are purge options available that allow them to be filled with a benign gas like N2, also they can sit in a stocker device filled with N2 instead of air if its a more cost effective way to achieve better yield/defects.

    Speaking generally, at most steps the wafers in a fab are in a state where exposure to air is not detrimental to their performance. There can be queue times enforced between steps to ensure they aren't sitting around exposed to air at critical steps. Wafers can be transferred in what's called a FOUP exchange, often used to segregate them between very incompatible portions of the process flow (e.g. Copper vs FEOL)

    Similarly the tools themselves have micro-environments that can be controlled for when the wafers are removed from the FOUPs for processing. I believe the door seals they use are a Thermoplastic elastomer. Using normal rubber gaskets would outgas or shed particles, both of which can kill a device. Here is a link to one of the largest manufacturers of FOUPs for the industry. https://www.entegris.com/shop/en/USD/Products/Wafe...

    The only EUV I've seen up close was fairly opened up, it was a development tool installed at SEMATECH in Albany. I'm glad they've come so far, there were a lot of questions for years about the infrastructure needed to support them (masks, pellicles, resist, sources, etc) thus why it's taken so long for them to be adopted much less put into production and we used double, triple, or more patterning on Immersion DUV instead.
  • ballsystemlord - Thursday, February 17, 2022 - link

    Awesome! Thanks!
  • kamak123 - Thursday, February 17, 2022 - link

    Is that it:

    https://www.intel.com/content/www/us/en/newsroom/n...
  • Arsenica - Thursday, February 17, 2022 - link

    From your description the half sphere must be the EUV source vacuum vessel. The "noble gas" lines are used for the tin droplet generator (needed for generating the tin plasma that emits EUV photons)

    I'm pretty sure that the vessel it's made out of austenitic stainless steel instead of aluminum.

    If you still haven't gone to IBM Albany ask them to see the underfab if you want to see a giant Laser (I think you can also see it from the lowest level of the eastern access stairs of NanoFab-X)
  • biigD - Friday, February 18, 2022 - link

    This is the kind of thing that makes me wish we could subscribe to anandtech - great article!
  • erickg - Wednesday, February 23, 2022 - link

    Great read as I walk through your path in the fab. The EUV machine in the fab is a strong physical representation of the cutting-edge semiconductor technology's existence.
  • James5mith - Friday, April 8, 2022 - link

    Great article.

    Didn't Ian quit Anandtech in February 2022?
    https://www.anandtech.com/show/17270/going-from-th...
  • rohityadav@145 - Monday, June 6, 2022 - link


    Godrej Meridien sector 106 [Luxury Apartment] at Dwarka Expressway

    This Godrej Meridien Three-storied structure has an impressive glass façade and house an array of sports and entertainment facilities.These are homes crafted for the select few with wellness, an active life and luxurious amenities.The 6132 sq. m. sprawling clubhouse, is one of the finest in Gurugram(Dwarka Expressway).

    Godrej Meridien sector 106
  • rohityadav@145 - Monday, June 6, 2022 - link


    Godrej Meridien sector 106 [Luxury Apartment] at Dwarka Expressway

    This Godrej Meridien Three-storied structure has an impressive glass façade and house an array of sports and entertainment facilities.These are homes crafted for the select few with wellness, an active life and luxurious amenities.The 6132 sq. m. sprawling clubhouse, is one of the finest in Gurugram(Dwarka Expressway).

    Godrej Meridien sector 106

    www.larisa.com

Log in

Don't have an account? Sign up now