Comments Locked

5 Comments

Back to Article

  • Tyns - Wednesday, August 8, 2018 - link

    So they have this breakthrough tech that puts cmos under the array using two wafers (IMFT did that with one wafer) that decreases time to market and cost even though its doubling(?) wafers (during an ongoing wafer shortage) and will more than double the IO speed of the most performant competitors’ products...

    ...but they’re open to collaboration instead of crushing their competitors...

    Hahahahahahah

    Oh, I forgot their 64L is almost as dense as competitors’ 96L, ignore that they’re not ramping any NAND yet since none of it is cost competitive.

    The Chinese memory industry is as yet a joke.
  • OwCH - Friday, August 10, 2018 - link

    Well, the major improvement is that they can choose whatever node suits their needs best for each part. For NAND-cells, smaller isn't always better, as we saw a few years ago. For the peripheral parts, smaller will nearly always be better.

    On paper, the concept is rational and would definitely lead to better performance. The question is if they can produce real world results.

    They are probably open for collab because their NAND-cell tech is way behind other manufacturers.
  • Nyte7 - Monday, August 13, 2018 - link

    lol wow someone didn't get laid last night. Did a Chinaman get a promotion over you or something lol?
  • jjj - Wednesday, August 8, 2018 - link

    Wish the part on staircase optimization had more details and clarity.
  • linuxgeex - Saturday, November 9, 2019 - link

    "06:12PM EDT - Putting the periphery above the stack"

    Oops, you mean below.

Log in

Don't have an account? Sign up now