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  • coburn_c - Monday, February 22, 2016 - link

    'ultra-low efficiency'

    I though AMD had that market sewn up?
  • coburn_c - Monday, February 22, 2016 - link

    Also, dropping 64-bit support is now an advancement?

    I told you so, I told you so, I told you so.
  • coburn_c - Monday, February 22, 2016 - link

    Also, also; does this mean that gentleman at Qualcomm can have his job back?
  • xdrol - Tuesday, February 23, 2016 - link

    If you don't use all 64 bit memory addresses, then AArch32 even could perform better than AArch64 with its smaller program footprint and memory/cache usage, and I guess both is a plus in the ultra-mega low power world. (Noticed that all categories are 'high' in marketing lingo?)
  • tuxRoller - Tuesday, February 23, 2016 - link

    It's not just addresses but registers, as well.
  • tuxRoller - Tuesday, February 23, 2016 - link

    OTOH, you could use the x32abi of the x64isa to get access to those additional registers without incurring the pointer penalty (ofc you also wouldn't have access to the 64bit address space).
  • extide - Wednesday, February 24, 2016 - link

    That's exactly what AArch32 in ARM v8 is.
  • 0x16a0 - Friday, February 26, 2016 - link

    No, ABI is separate to the architecture. The equivalent of x32 ABI for ARM is ILP32.

    AArch32 has 32 bit registers and 32 bit pointers.
  • kgardas - Tuesday, February 23, 2016 - link

    I don't think so, the reason is bigger register set on AArch64. You used word "perform" so I've thought this is from pure performance point of view. On the other hand efficiency is another thing to consider here, and that's what A32 is about...
  • boeush - Tuesday, February 23, 2016 - link

    Kinda crazy, next thing you know, they'll start making mobile devices with reasonable screen resolutions again - achieving earth-shattering improvements in performance, battery life, and efficiency...
  • Kylinblue - Tuesday, February 23, 2016 - link

    You really need 64bit for IoT?
  • Ryan Smith - Monday, February 22, 2016 - link

    Heh, that's what happens when "low power" and "high efficiency" get merged with too few words. Thanks for pointing that out.
  • blaktron - Monday, February 22, 2016 - link

    I'm in my early 30s and I have owned CPUs built with transistors larger than this core...
  • extide - Monday, February 22, 2016 - link

    Ehh, close, but not quite! 0.25mm is 250um -- the biggest processes were about 10um, (which is, 10,000nm, we have come a long way!) For example, the Intel 4004, the first processor, was made on 10um.
  • jas90 - Monday, February 22, 2016 - link

    So by that logic extide,at 10nm a single core would be 61um if Tsmc 10nm is 4.1 times smaller than the 28HPC giving the example in the slide,getting close ;)
  • ant6n - Tuesday, February 23, 2016 - link

    Even worse: 0.25mm² = (0.5mm)²
  • r3loaded - Monday, February 22, 2016 - link

    ""Is this an A35 with 64-bit 'slashed off'?" While ARM chuckled at my oversimplification, they agreed that from a very high-level perspective that it could be considered as an accurate description of the A32."

    That's literally what it is, when you absolutely must squeeze out every last drop out of your area and power budget.

    There will also shortly be a 64-bit only version of the A35 which has AArch32 support slashed off, again to save on power and area. Might be useful for someone...
  • name99 - Monday, February 22, 2016 - link

    Are you claiming this (64-bit only version of the A35) as a joke, or do you have actual knowledge of this?
    I expect that Apple's watch CPU would take this path. They have already abstracted 3rd party code submissions to an IR form, so it's possible (I honestly don't know) that that IR is abstract enough that it could just be rendered down to 64-bits even though it was compiled as 32-bits. If so, there would really be no reason for Apple to ever provide a simultaneously 32 and 64-bit watch CPU.

    However it is hard to see watches (or anything else in the very low power category) as really wanting 64-bits in the near (three-year or so) future. Is there reason to believe that using the 64-bit ISA would provide something desirable (better power efficiency or smaller code) than using the 32-bit bit ISA and Thumb-2? Obvious the 64-bit ISA provides improved performance in various ways (especially if you use address bits for tagging) but for these devices right now, I think performance/watt is more important than just performance, and I don't know if the improved 64-bit ISA efficiency can make up for the work done on wider registers.
  • r3loaded - Tuesday, February 23, 2016 - link

    It's not 100% confirmed for release but it is a real product. I believe that certain customers are interested in a low-power A-class system control processor that will form part of an existing 64-bit system while minimising area for the primary cores. Since such a processor would be guaranteed to only run 64-bit ARMv8-A code, AArch32 support would be unnecessary.

    It's a niche thing but it could happen. No idea what the final name will be.
  • RobATiOyP - Tuesday, February 23, 2016 - link

    Would AArch64 only reduce area by much? 64bit CPU still needs to handle 8/16/32 bit quantities as well as 64bits, so seems like only instruction decode would be simplified.
  • Dmcq - Wednesday, February 24, 2016 - link

    A 64 bit only processor certainly sounds a good idea to me for embedded processors where performance is critical. the instruction set is more efficient and cleaner and it would get rid of a lot of cruft.

    The cruft though is probably what makes the 32 bit ARM version the choice for a chopped down version at the moment. It has instructions that do part of what the SIMD instructions do so the degradation from removing the SIMD isn't quite as bad as it might be, and it has the Thumb-2 instruction set which is more compact than other 32 bit processors. Plus there is a lot of embedded code already developed for it.

    To get something similarly tiny with the 64 bit you'd need to add the SIMD in general register type DSP instructions and a compact Thumb like encoding and a flag to say ignore the top 32 bits in address calculations probably wouldn't go amiss either to get round possible funnies. It doesn't sound pretty so I think it is 32 bit ARM for the very low end for quite a while yet.
  • extide - Monday, February 22, 2016 - link

    I like this core, although I hate that they called it the A32 -- it's too confusing with AArch32 and stuff. I mean in a way it is fitting, as it is 32bit, but ehh.
  • Floyd42 - Tuesday, February 23, 2016 - link

    So, what's the code name of this core? Mercury was the only one they published in this low end area, but this is taken already for the A-35.
  • Manabu - Wednesday, February 24, 2016 - link

    Ceres? :P
  • zugzug1 - Thursday, March 31, 2016 - link

    minerva
  • MrSpadge - Tuesday, February 23, 2016 - link

    Perfect for the new 16 core smartphones for the asian market, which are still going to be outperformed by 2 of Apples cores.
  • kreacher - Saturday, February 25, 2017 - link

    What's happening with A-32/35? It's been an year and new Android Wear 2.0 smart watches are still being released with A-7 (SnapDragon 2100).
    I was hoping to buy a smart watch this year with decent battery life and performance (A-35/32 on 10nm) but it looks like wearables still need a couple more generations to mature.

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