Broadwell in a Server SoC

In a nutshell, the Xeon D-1540 is two silicon dies in one highly integrated package. Eight 14 nm Broadwell cores, a shared L3-cache, a dual 10 gigabit MAC, a PCIe 3.0 root with 24 lanes find a home in the integrated SoC whereas in the same package we find four USB 3.0, four USB 2.0, six SATA3 controllers and a PCIe 2.0 root integrated in a PCH chip.

 

The Broadwell architecture brings small microarchitectural improvements - Intel currently claims about 5.5% higher IPC in integer processing. Other improvements include slightly lower VM exit/enter latencies, something that Intel has been improving with almost every recent generation (excluding Sandy Bridge). 

Of course, if you are in the server business, you care little about all the small IPC improvements. Let us focus on the large relevant improvements. The big improvements over the Xeon E3-1200 v3 are:

  1. Twice as many cores and threads (8/16 vs 4/8)
  2. 32 GB instead of 8 GB per DIMM supported and support for DDR4-2133
  3. Maximum memory capacity has quadrupled (128 GB vs 32 GB)
  4. 24 PCIe 3.0 lanes instead of 16 PCIe 3.0 lanes
  5. 12 MB L3 rather than 8 MB L3
  6. No separate C22x chipset necessary for SATA / USB
  7. Dual 10 Gbit Ethernet integrated ...

And last but not least, RAS (Reliability, Availability and Servicability) features which are more similar to the Xeon E5:

The only RAS features missing in the Xeon D are the expensive ones like memory mirroring. Those RAS features a very rarely used, and The Xeon D can not offer them as it does not have a second memory controller. 

Compared to the Atom C2000, the biggest improvement is the fact that the Broadwell core is vastly more advanced than the Silvermont core. That is not all: 

  1. Atom C2000 had no L3-cache, and are thus a lot slower in situation where the cores have to sync a lot (databases)
  2. No support for USB 3 (Xeon D: four USB 3 controllers)
  3. As far as we know Atom C2000 server boards were limited to two 1 Gbit PHYs (unless you add a separate 10 GBe controller)
  4. No support for PCIe 3.0, "only" 16 PCIe Gen2 lanes. 

There are more subtle differences of course such as using a crossbar rather than a ring, but those are beyond the scope of this review.  

The Xeon D SoC Meet the SuperServer 5028D-TN4T
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  • extide - Tuesday, June 23, 2015 - link

    That's ECC Registered, -- not sure if it will take that, but probably, although you dont need registered, or ECC. Reply
  • nils_ - Wednesday, June 24, 2015 - link

    If you want transcoding, you might want to look at the Xeon E3 v4 series instead, which come with Iris Pro graphics. Should be a lot more efficient. Reply
  • bernstein - Thursday, June 25, 2015 - link

    for using ECC UDIMMs, a cheaper option would be an i3 in a xeon e3 board. Reply
  • psurge - Tuesday, June 23, 2015 - link

    Has Intel discussed their Xeon-D roadmap at all? I'm wondering in particular if 2x25GbE is coming, whether we can expect a SOC with higher clock-speed or more cores (at a higher TDP), and what the timeframe is for Skylake based cores. Reply
  • nils_ - Tuesday, June 23, 2015 - link

    Is 25GbE even a standard? I've heard about 40GbE and even 56GbE (matching infiniband), but not 25. Reply
  • psurge - Tuesday, June 23, 2015 - link

    It's supposed be a more cost effective speed upgrade to 10GbE than 40GbE (it uses a single 25Gb/s serdes lane, as used in 100GbE, vs 4 10Gb/s lanes), and IIRC is being pushed by large datacenter shops like Google and Microsoft. There's more info at http://25gethernet.org/. I'm not sure where things are in the standardization process. Reply
  • nils_ - Wednesday, June 24, 2015 - link

    It also has an interesting property when it comes to using a breakout cable of sorts, you could connect 4 servers to 1 100GbE port (this is already possible with 40GbE which can be split into 4x10GbE). Reply
  • JohanAnandtech - Wednesday, June 24, 2015 - link

    Considering that the Xeon D must find a home in low power high density servers, I think dual 10 Gbit will be standard for a while. Any idea what 25/40 Gbit PHY would consume? Those 10 Gbit PHYs already need 3 Watt in idle, probably around 6-8W at full speed. That is a large chunk of the power budget in a micro/scale out server. Reply
  • psurge - Wednesday, June 24, 2015 - link

    No I don't, sorry. But, I thought SFP+ with SR optics (10GBASE-SR) was < 1W per port, and that SFP+ direct attach (10GBASE-CR) was not far behind? 10GBASE-T is a power hog... Reply
  • pjkenned - Tuesday, June 23, 2015 - link

    Hey Johan - just re-read. A few quick thoughts:
    First off - great piece. You do awesome work. (This is Patrick @ ServeTheHome.com btw)

    Second - one thing should probably be a bit clearer - you were not using a Xeon D-1540. It was a ES Broadwell-DE version at 2.0GHz. The shipping product has 100MHz higher clocks on both base and max turbo. I did see a 5% or so performance bump from the first ES version we tested to the shipping parts. The 2.0GHz parts are really close to shipping spec though. One both of my pre-release Xeon D and all of the post-release Xeon D systems was nearly identical.

    Those will not change your conclusions but does make the actual Intel Xeon D-1540 a bit better than the one you tested. LMK if you want me to set aside some time on a full speed version on a Xeon D-1540 system for you.
    Reply

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