Core Architecture Changes

Ivy Bridge is considered a tick from the CPU perspective but a tock from the GPU perspective. On the CPU core side that means you can expect clock-for-clock performance improvements in the 4 - 6% range. Despite the limited improvement in core-level performance there's a lot of cleanup that went into the design. In order to maintain a strict design schedule it's not uncommon for a number of features not to make it into a design, only to be added later in the subsequent product. Ticks are great for this.

Five years ago Intel introduced Conroe which defined the high level architecture for every generation since. Sandy Bridge was the first significant overhaul since Conroe and even it didn't look very different from the original Core 2. Ivy Bridge continues the trend.

The front end in Ivy Bridge is still 4-wide with support for fusion of both x86 instructions and decoded uOps. The uOp cache introduced in Sandy Bridge remains in Ivy with no major changes.

Some structures within the chip are now better optimized for single threaded execution. Hyper Threading requires a bunch of partitioning of internal structures (e.g. buffers/queues) to allow instructions from multiple threads to use those structures simultaneously. In Sandy Bridge, many of those structures are statically partitioned. If you have a buffer that can hold 20 entries, each thread gets up to 10 entries in the buffer. In the event of a single threaded workload, half of the buffer goes unused. Ivy Bridge reworks a number of these data structures to dynamically allocate resources to threads. Now if there's only a single thread active, these structures will dedicate all resources to servicing that thread. One such example is the DSB queue that serves the uOp cache mentioned above. There's a lookup mechanism for putting uOps into the cache. Those requests are placed into the DSB queue, which used to be split evenly between threads. In Ivy Bridge the DSB queue is allocated dynamically to one or both threads.

In Sandy Bridge Intel did a ground up redesign of its branch predictor. Once again it doesn't make sense to redo it for Ivy Bridge so branch prediction remains the same. In the past prefetchers have stopped at page boundaries since they are physically based. Ivy Bridge lifts this restriction.

The number of execution units hasn't changed in Ivy Bridge, but there are some changes here. The FP/integer divider sees another performance gain this round. Ivy Bridge's divider has twice the throughput of the unit in Sandy Bridge. The advantage here shows up mostly in FP workloads as they tend to be more computationally heavy.

MOV operations can now take place in the register renaming stage instead of making it occupy an execution port. The x86 MOV instruction simply copies the contents of a register into another register. In Ivy Bridge MOVs are executed by simply pointing one register at the location of the destination register. This is enabled by the physical register file first introduced in Sandy Bridge, in addition to a whole lot of clever logic within IVB. Although MOVs still occupy decode bandwidth, the instruction doesn't take up an execution port allowing other instructions to execute in place of it.

ISA Changes

Intel also introduced a number of ISA changes in Ivy Bridge. The ones that stand out the most to me are the inclusion of a very high speed digital random number generator (DRNG) and supervisory mode execution protection (SMEP).

Ivy Bridge's DRNG can generate high quality random numbers (standards compliant) at 2 - 3Gbps. The DRNG is available to both user and OS level code. This will be very important for security and algorithms going forward.

SMEP in Ivy Bridge provides hardware protection against user mode code being executed in more privileged levels.

Motherboard & Chipset Support Cache, Memory Controller & Overclocking Changes
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  • shiznit - Saturday, September 17, 2011 - link

    Intel's APU is more integrated than AMD's
  • TypeS - Monday, September 19, 2011 - link

    Guess you're one of those fanboys that just couldn't come back down from high of AMD's time in the spotlight with the Athlon 64?

    For someone who speaks of facts, you need to go check the architecture of both the SNB and Llano/Brazo cores before you say AMD has the more integrated approach.

    AMD is just using marketing nonsense with calling their new CPU an "APU", just like when they called the Phenom X4s "true quad cores".
  • JonnyDough - Monday, September 19, 2011 - link

    Marketing fluff is Intel's bag, right? Maybe you forget the whole "clock speed" fiasco. Selling P4's claiming they are faster than the competition, although they are not...

    At least consumers eventually caught on and OEMs began looking at AMD processors as well. :)

    You all sound like fanboys though, who really cares who's right? We should just be excited about the TECH!
  • Kaihekoa - Saturday, September 17, 2011 - link

    Lol with Intel's capital and recruiting experienced GPU engineers that "two year lead" will evaporate faster than boiling water. I don't know where you're getting your delusions of the mainstream market sapping up AMD's CPU/GPU combination marketing and products, but the average computer user doesn't use or need anything more than Intel's current generation of graphics. And as others have mentioned Intel's design is more integrated than AMDs on an engineering/design level.

    Yes, they have the more powerful GPU, but you have to be an idiot to think it's more integrated than Ivy Bridge. CPU performance and graphics good enough to power 2D and 3D accelerated media are the yardstick for PC performance for the vast majority of users. You're truly deluding yourself if you think the average computer user is playing The Witcher 2 and Deus Ex on their PCs with cards more powerful than IVB's. Even now with AMD's two year advantage, guess who owns the market for systems with a combined CPU/GPU? For integrated graphics? Wintel.

    Am I an Intel fanboy? No, the last desktop system I built had an AMD CPU and discrete GPU, but you can't logically deny how well their business is doing now, and you'd be a food to think they would overlook the mainstream demand for a high-end APU. In the future when the market needs/wants it, Intel will have something equivalent or better to AMD/ATI.
  • Zoomer - Saturday, September 17, 2011 - link

    Let's not forget drivers and game support, not to mention IQ. Last I checked, Intel graphics drivers were still pretty horrible.
  • iwodo - Sunday, September 18, 2011 - link

    Exactly. Designing Hardware is easy. You throw Money and Engineers you could be there in no time. Especially with the expertise from Intel.

    Software - on the other hand, takes time. No matter how many engineers you put in. Drivers is the problems Intel has to overcome.
  • JonnyDough - Monday, September 19, 2011 - link

    I agree. Software is key. Intel is good at parts of it, AMD is better when it comes to keeping up with game developers. However, business markets make enthusiast markets look miniscule. Still, both are great competitors and we consumers just keep winning. :)
  • iwodo - Sunday, September 18, 2011 - link

    I forgot to add, there is a reason why Nvidia has more Software Engineers then Hardware.
  • medi01 - Sunday, September 18, 2011 - link

    It's actually the other way round. Pretty much any CPU starting from about 2008 is "more than good enough" for most users.
  • BSMonitor - Sunday, September 18, 2011 - link

    "In spite of the marketing hype from Intel it looks like they've conceded that AMD has the better system approach with APUs for mainstream consumers and laptops. CPU performance alone is no longer a valid yardstick for PC performance thanks to AMD's advance thinking and Llano. "

    This is utter nonsense. All AMD has done is transfer 400 of its shader units on to the CPU core. What you have with AMD is a 4-5 year old GPU combined with a 3 year old CPU.

    Both sides of the coin yeild a huge YAWN from anyone looking for real performance.

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