This week Intel held its annual Architecture Day event for select press and partners. As with previous iterations, the company disclosed details about its next generation architectures set to come to the market over the next twelve months. Intel has promised the release of its next-generation consumer and mobile processor family, Alder Lake, to come by the end of the year and today the company is sharing a good number of details about the holistic design of the chips as well as some good detail about the microarchitectures that form this hybrid design: Golden Cove and Gracemont. Here is our analysis of Intel’s disclosure.

Alder Lake: Intel 12th Gen Core

As mentioned in previous announcements, Intel will launch its Alder Lake family of processors into both desktop and mobile platforms under the name of Intel’s 12th Gen Core Processors with Hybrid Technology later this year. This is Intel’s second generation hybrid architecture built on Intel 7 process node technology. The hybrid design follows Intel Lakefield designs for small notebooks launched last year. The nature of a hybrid design in Intel nomenclature involves having a series of high ‘Performance’ cores paired with a number of high ‘Efficiency’ cores. Intel has simplified this into P-core and E-core terminology.

For Alder Lake, the processor designs feature Performance cores based on a new Golden Cove microarchitecture, and Efficiency cores based on a new Gracemont architecture. We will cover both over the course of this article, however the idea is that the P-core is preferential for single threaded tasks that require low latency, and the E-core is better in power limited or multi-threaded scenarios. Each Alder Lake SoC will physically contain both, however Intel has not yet disclosed the end-user product configurations.

Each of the P-cores has the potential to offer multithreading, whereas the E-cores are one thread per core. This means there will be three physical designs based on Alder Lake:

  • 8 P-core + 8 E-core (8C8c/24T) for desktop on a new LGA1700 socket
  • 6 P-core + 8 E-core (6C8c/20T) for mobile UP3 designs
  • 2 P-core + 8 E-core (2C8c/12T) for mobile UP4 designs

Intel typically highlights UP4 mobile designs for very low power installs, down to 9 W, whereas UP3 can cover anything from 12 W to 35 W (or perhaps higher), but when asked about the power budgets for these processors, Intel stated that more detail will follow when product announcements are made. Intel did confirm that the highest client power, presumably on the desktop processor, will be 125 W.

Highlighted in our discussions is how modular Intel has made Alder Lake. From a range of base component options, the company mixed and matched what it felt were the best combination of parts for each market.

Here it shows that four E-cores takes up the same physical space as one P-core, but also that the desktop hardware will at most have 32 EUs (Execution Units) for Xe-LP graphics (same as the previous generation), while both of the mobile processors will offer 96 physical EUs that may be disabled down based on the specific line item in the product stack.

All three processors will feature Intel’s next generation Gaussian Neural Accelerator (GNA 3.0) for minor low power AI tasks, a display engine, and some level of PCIe, however the desktop processor will have more. Only the mobile processors will get an Image Processing Unit (IPU), and Thunderbolt 4 (TBT), and here the big UP3 mobile processor gets four ports of Thunderbolt whereas the smaller UP4 will only get two. The desktop processor will not have any native Thunderbolt connectivity.

A bit more info on the Desktop Processor IO and Interconnect

We’ll cover a bit more detail about the core designs later in this article, but Intel did showcase some of the information on the desktop processor. It confirmed explicitly that there would be 16 total cores and 24 threads, with up to 30 MB of non-inclusive last level/L3 cache.

In contrast to previous iterations of Intel’s processors, the desktop processor will support all modern standards: DDR5 at 4800 MT/s, DDR4-3200, LPDDR5-5200, and LPDDR4X-4266. Alongside this the processor will enable dynamic voltage-frequency scaling (aka turbo) and offer enhanced overclocking support. What exactly that last element means we’re unclear of at this point.

Intel confirmed that there will not be separate core designs with different memory support – all desktop processors will have a memory controller that can do all four standards. What this means is that we may see motherboards with built-in LPDDR5 or LPDDR4X rather than memory slots if a vendor wants to use LP memory, mostly likely in integrated small form factor designs but I wouldn’t put it past someone like ASRock to offer a mini-ITX board with built in LPDDR5. It was not disclosed what memory architectures the mobile processors will support, although we do expect almost identical support.

On the PCIe side of things, Alder Lake’s desktop processor will be supporting 20 lanes of PCIe, and this is split between PCIe 4.0 and PCIe 5.0.

The desktop processor will have sixteen lanes of PCIe 5.0, which we expect to be split as x16 for graphics or as x8 for graphics and x4/x4 for storage. This will enable a full 64 GB/s bandwidth. Above and beyond this are another four PCIe 4.0 lanes for more storage. As PCIe 5.0 NVMe drives come to market, users may have to decide if they want the full PCIe 5.0 to the discrete graphics card or not

Intel also let it be known that the top chipset for Alder Lake on desktop now supports 12 lanes of PCIe 4.0 and 16 lanes of PCIe 3.0. This will allow for additional PCIe 4.0 devices to use the chipset, reducing the number of lanes needed for items like 10 gigabit Ethernet controllers or anything a bit spicier. If you ever thought your RGB controller could use more bandwidth, Intel is only happy to provide.

Intel did not disclose the bandwidth connectivity between the CPU and the chipset, though we believe this to be at least PCIe 4.0 x4 equivalent, if not higher.

The Alder Lake processor retains the dual-bandwidth ring we saw implemented in Tiger Lake, enabling 1000 GB/s of bandwidth. We learned from asking Intel in our Q&A that this ring is fully enabled regardless of whether the P-cores or E-cores are being used – Intel can disable one of the two rings when less bandwidth is needed, which would save power, however based on previous testing this single ring could end up drawing substantial power compared to the E-cores in low power operation. (This may be true in the mobile processors as well, which would have knock on effects for mobile battery life.)

The 64 GB/s of IO fabric is in line with the PCIe 5.0 x16 numbers we saw above, however the 204 GB/s of memory fabric bandwidth is a confusing number. Alder Lake features a 128-bit memory bus, which allows for 4x 32-bit DDR5 channels (DDR5 has two 32-bit channels per module, so 2 modules still), however in order to reach 204 GB/s in that configuration requires DDR5-12750; Intel has rated the processor only at DDR5-4800, less than half that, so it is unclear where this 204 GB/s number comes from. For perspective, Intel’s Ice Lake does 204.8 GB/s, and that’s a high-power server platform with 8 channels of DDR4-3200.

This final slide mentions TB4 and Wi-Fi 6E, however as with previous desktop processors, these are derived from controllers attached to the chipset, and not in the silicon itself. The mobile processors will have TBT integrated, but the desktop processor does not.

This slide also mentions Intel Thread Director, which we want to address on the next page before we get to the microarchitecture analysis.

Intel Thread Director
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  • mode_13h - Thursday, August 19, 2021 - link

    > On the E-core side, Gracemont will be Intel’s first Atom processor to support AVX2.

    Finally. It's about f'ing time, Intel.

    > desktop processors and mobile processors will now have AVX-512 disabled in all scenarios.
    > ...
    > If AMD’s Zen 4 processors plan to support some form of AVX-512 ... we might be in
    > some dystopian processor environment where AMD is the only consumer processor
    > on the market to support AVX-512.

    LOL! Exactly! I wouldn't call it "dystopian", exactly. Just paradoxical.

    And now that Intel has been pushing AVX-512 adoption for the past 5 years, there should actually be a fair amount of software & libraries that can take advantage of it, making this the worst possible time for Intel to step back from AVX-512! Oh, the irony would be only too delicious!

    > Intel is also integrating support for VNNI instructions for neural network calculations.
    > In the past VNNI (and VNNI2) were built for AVX-512, however this time around Intel
    > has done a version of AVX2-VNNI for both the P-core and E-core designs in Alder Lake.

    Wow. That really says a lot about what a discombobulated mess the development of Alder Lake must've been! They thought the E-cores would be a good area-efficient way to add performance, but then AVX-512 probably would've spoiled that. So, then they had to disable AVX-512 in the P-cores. But, since that would hurt deep learning performance too much, they had to back-port VNNI to AVX2!

    And then, we're left to wonder how much software is going to bother supporting it, just for this evolutionary cul-de-sac of a CPU (presumably, Raptor Lake or Meteor Lake will finally enable AVX-512 in the E-cores).
    Reply
  • Gondalf - Thursday, August 19, 2021 - link

    Have you realized this SKU was thinked for 7nm ??....and than backported to 10nm ???.
    Rocket Lake number two.
    Reply
  • TomWomack - Thursday, August 19, 2021 - link

    VNNI is four very straightforward instructions (8-bit and 16-bit packed dot-product with/without saturation), so the back port is unlikely to have been difficult Reply
  • mode_13h - Thursday, August 19, 2021 - link

    Yeah, but it implies some chaos in the design process.

    Also, my question about how well-supported it will be stands. I think a lot of people aren't going to go back and optimize their AVX2 path to use it. Any focus on new instructions is likely to focus on AVX-512.
    Reply
  • Spunjji - Monday, August 23, 2021 - link

    If they kill AVX-512 in consumer with ADL only to bring it back in the next generation, I shall be laughing a hearty laugh. Another round of "developer relations" funding will be needed...

    Personally I think they never should have brought it to consumer.
    Reply
  • mode_13h - Tuesday, August 24, 2021 - link

    > I think they never should have brought it to consumer.

    I have my gripes against AVX-512 (mostly, with regard to the 14 nm implementation), but it's not all bad. I've read estimates that it only adds 11% to the core size of Skylake-SP (excluding the L3 cache slice & such). It was estimated at about 5% of a Skylake-SP compute tile. So, that means less than 5% of the total die size. So, it's probably not coming at too high a price.
    Reply
  • Spunjji - Friday, August 27, 2021 - link

    That's fair - my reasons for thinking they shouldn't have done it are more related to marketing and engineering effort than die space, though.

    They put in a lot of time and money to bring a feature to a market that didn't really need it, including doing a load of "developer relations" stuff to develop some cringe-worthy edge-case benchmark results, alongside a bunch of slightly embarrassing hype (including the usual sponsored posters on comment sections), all to lead up to this quiet little climb-down.

    Seems like to me like it would have made more sense to designate it as an Enterprise Grade feature - an excuse to up-sell from the consumer-grade "Xeon" processors - and then trickle it down to consumer products later.
    Reply
  • mode_13h - Saturday, August 28, 2021 - link

    > Seems like to me like it would have made more sense to designate it as an Enterprise
    > Grade feature ... and then trickle it down to consumer products later.

    Yeah, that's basically what they did. They introduced it in Skylake-SP (if we're not counting Xeon Phi - KNL), and kept it out of consumers' hands until Ice Lake (laptop) and Rocket Lake (desktop). It seems pretty clear they didn't anticipate having to pull it back, in Alder Lake, when the latter two were planned.
    Reply
  • mode_13h - Saturday, August 28, 2021 - link

    BTW, you know the Skylake & Cascade Lake HEDT CPUs had it, right? So, the whole up-sell scheme is what they *actually* did! Reply
  • TristanSDX - Thursday, August 19, 2021 - link

    If ADL have disbaled features like part of L2 cache or without AVX-512, so it is interesting if presented 19% IPC growth apply to ADL or SPR.
    AMD Zen 3 will definitelly have AVX-512, BIG shame on you, for disabling it, even for SKU without small cores
    Reply

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