The Cortex-A710: More Performance with More Efficiency

While the Cortex-X2 goes for all-out performance while paying the power and area penalties, Arm's Cortex-A710 design goes for a more efficient approach.

First of all, the new product nomenclature now is self-evident in regards to what Arm will be doing going forward- they’re skipping the A79 designation and simply starting fresh with a new three-digit scheme with the A710. Not very important in the grand scheme of things but an interesting marketing tidbit.

The Cortex-A710, much like the X2, is an Armv9 core with all new features that come with the new architecture version. Unlike the X2, the A710 also supports EL0 AArch32 execution, and as mentioned in the intro, this was mostly a design choice demanded by customers in the Chinese market where the ecosystem is still slightly lagging behind in moving all applications over to AArch64.

In terms of front-end enhancements, we’re seeing the same branch prediction improvements as on the X2, with larger structures as well as better accuracy. Other structures such as the L1I TLB have also seen an increase from 32 entries to 48 entries. Other front-end structures such as the macro-OP cache remain the same at 1.5K entries (The X2 also remains at 3K entries).

A very interesting choice for the A710 mid-core is that Arm has reduced the macro-OP cache and dispatch stage throughputs from 6-wide to 5-wide. This was mainly a targeted power and efficiency optimization for this generation, as we’re seeing a more important divergence between the Cortex-A and Cortex-X cores in terms of their specializations and targeted use-cases for performance and power.

The dispatch stage also features the same optimizations as on the X2, removing 1 cycle from the pipeline towards an overall 10-cycle pipeline design.

Arm also focuses on core improvements that affect the uncore parts of the system, which take place thanks to the new improvements in the prefetcher designs and how they interact with the new DSU-110 (which we’ll cover later). The new combination of core and DSU are able to reduce access from the core towards the L3 cache, as well as reducing the costly DRAM accesses thanks to the more efficiency prefetchers and larger L3 cache.

In terms of IPC, Arm advertises +10%, but again the issue with this figure here is that we’re comparing an 8MB L3 cache design to a 4MB L3 cache design. While this is a likely comparison for flagship SoCs next year, because the Cortex-A710 is also a core that would be used in mid-range or lower-end SoCs which might use much smaller L3 caches, it’s unlikely we’ll be seeing such IPC improvements in that sector unless the actual SoCs really do also improve their DSU sizes.

More important than the +10% improvement in performance is that, when backing off slightly in frequency, we can see that the power reduction can be rather large. According to Arm, at iso-performance the A710 consumes up to 30% less power than the Cortex-A78. This is something that would greatly help with sustained performance and power efficiency of more modestly clocked “middle” core implementations of the Cortex-A710.

In general, both the X2 and the A710’s performance and power figures are quite modest, making them the smallest generation-over-generation figures we’ve seen from Arm in quite a few years. Arm explains that due to this generation having made larger architectural changes with the move to Armv9, there has been an impact in regards to the usual efficiency and performance improvements that we’ve seen in prior generations.

Both the X2 and the A710 are also the fourth generation of this Austin microarchitecture family, so we’re hitting a wall of diminishing returns and maturity of the design. A few years ago we were under impression that the Austin family would only go on for three generations before handing things over to a new clean-sheet design from the Sophia team, but that original roadmap has been changed, and now we'll be seeing the new Sophia core with larger leaps in performance being disclosed next year.

The Cortex-X2: More Performance, Deeper OoO The Cortex-A510: Brand-new Little Design Comes in Pairs
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  • ChrisGX - Thursday, May 27, 2021 - link

    Yes, @melgross, @mattbe and @mode_13h are absolutely right. Apple has an architectural license from ARM, viz. a license for the ARM ISA rather than any physical IP. Not deterred by that some individuals commenting here seem to want to suggest that Apple has infringed on ARM's IP or somehow by nefarious means has acquired crucial information about proprietary tech found in ARM chips without stumping up the cash for it. These suggestions are pathetic. If a patent infringement is being alleged please tell us the patent number so that we can determine for ourselves whether there really has been a patent infringement. Or, is a criminal conspiracy with other parties to steal trade secrets from ARM being asserted? There is an obvious problem with that idea. Does anyone seriously suppose that ARM would fail to have Apple before a court demanding a huge settlement for theft of trade secrets, if it had any reason to think that Apple had been engaged in such an exercise? Uninformed individuals are just making up things that chime with their sense of how things must be. Hmm...here's a thought. If you know so little about a topic that you wouldn't be willing to stake your reputation on it or swear to in a court, say, then perhaps saying nothing on the topic would be a better choice than pretending to possess knowledge that you so obviously don't possess. Reply
  • mode_13h - Saturday, May 29, 2021 - link

    > Uninformed individuals are just making up things that chime with
    > their sense of how things must be.

    Welcome to the world of internet comment forums.

    > If you know so little about a topic that you wouldn't be willing to stake your reputation on it

    We don't do "reputation". Everybody is on equal footing, here. Just challenge them with facts, references, and sound logic.
    Reply
  • jeremyshaw - Tuesday, May 25, 2021 - link

    Thanks SarahKerrigan, igor velky. I was mostly thinking of configurations we didn't commonly see. We have seen 4xLITTLE, 2xbig.4xLITTLE, etc even the 8xA78C. The slides on page 5 cover setups we have seen before. Mostly curious if the fabric is tied to specific configs like was implied at the 8xA78C launch, or if it's flexible enough to have, say, two X2, two A710, four A510, or something like one X2 with four A510 (like Intel's Lakefield), etc. IMO, there are a lot of embedded controllers that don't need a lot of CPU throughput, but can benefit from one faster core for UI. Reply
  • Kangal - Saturday, May 29, 2021 - link

    I'm more interested in seeing a 3+5 design.

    The "Large Cores" just aren't good on a phone, a tablet maybe, not on a phone. We're already getting throttling on the "Medium Cores" (eg Cortex A78/A710). And most tasks on Android are handled great in Dualcore mode, and very few in Quad-core mode, when looking at the schedulers. So Three Medium Cores will offer 95% of the performance of your regular flagship processor. Extending the Small Cores to a group of five, also can help efficiency by having more performance in the lower zone, reducing the amount of times the large cores need to be stressed.

    However, with what was announced today, we can actually expect a REDUCTION in 2022 ARM processors compared to 2021 ARM processors. I mean we're talking about 10% gains in X2, 10% gains in A710, and 1% gains in A510, when compared to a design that should be on a better node with better cache. That's not guaranteed with the continuing Chip Shortage. IN FACT most chipmakers are willing to "cheap out" and simply use the marketing of "running on ARMv9" to justify the higher cost and lower performance.

    They stuffed up with the naming scheme btw. And they really stuffed up by not removing 32-bit support completely. And they stuffed up with not doing a blank-sheet approach, for a revolutionary ARMv9 design. We're going to see the smallest gains in Android Phones, just like it happened when people were comparing the QSD 800/801/805 to the QSD 808/810 (Cortex A57) back in 2015. Which hopefully means ARMs other divisions in UK/France can pick the slack and come with a proper successor. This would be the Cortex A72 to their Cortex A57, a la, 2022 A710 versus the 2023 A730. Though I doubt the little cores will get any improvement besides a 10% bump due to the node lithography improvements.
    Reply
  • psychobriggsy - Monday, June 21, 2021 - link

    Theoretically this should support 16 A510s (8 clusters), as each cluster shares a port on the interconnect.

    We may see 2X 4B 4L configurations (10 cores) one day, but in the main I guess we're stuck with 1X 3B 4L (8L?) options. I see budget chips using 4L+4L (wider FP on some).

    Wonder if there's room for an A310 chip (4 int cores per cluster, 1 shared FP, 2-wide).
    Reply
  • docola - Tuesday, May 25, 2021 - link

    does the shift to 64 bit cpus and apps mean that todays phone will start
    becoming obsolete starting next year?
    Reply
  • iphonebestgamephone - Tuesday, May 25, 2021 - link

    If you are on a 32 bit phone yeah Reply
  • docola - Tuesday, May 25, 2021 - link

    fun... so this means i shouldnt buy an expensive phone for another 1 or 2 years,
    because this is gonna be one of those rare REAL shift in tech... sigh....
    Reply
  • supdawgwtfd - Tuesday, May 25, 2021 - link

    Current phones support 64bit instructions...

    No need to delay.
    Reply
  • docola - Tuesday, May 25, 2021 - link

    great thanks! i know i sound ignorant in here oh well Reply

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