SK Hynix: We're Planning for DDR5-8400 at 1.1 Voltsby Gavin Bonshor on April 3, 2020 1:15 PM EST
Back in November last year, we reported that SK Hynix had developed and deployed its first DDR5 DRAM. Fast forward to the present, and we also know SK Hynix has recently been working on its DDR5-6400 DRAM, but today the company has showcased that it has plans to offer up to DDR5-8400, with on-die ECC, and an operating voltage of just 1.1 Volts.
WIth CPU core counts rising with the fierce battle ongoing between Intel and AMD in the desktop, professional, and now mobile markets, the demand to increase throughput performance is high on the agenda. Memory bandwidth by comparison has not been increasing as much, and at some level the beast needs to be fed. Announcing more technical details on its official website, SK Hynix has been working diligently on perfecting its DDR5 chips with capacity for up to 64 Gb per chip.
SK Hynix had previously been working on its DDR5-6400 DRAM, which has 16 Gb which is formed of 32 banks, with 8 bank groups, with double the available bandwidth and access potential when compared with DDR4-3200 memory. For reference, DDR4 uses 16 banks with 4 bank groups. The key solution to improve access throughout is the burst length, which has been doubled to 16 when compared with 8 on DDR4. Another element to consider is DDR4 can't by proxy run operations while it's refreshing. DDR5 is using SBRF (same bank refresh function) which allows the system the ability to use other banks while one is refreshing, which in theory improves memory access availability.
As we've already mentioned, SK Hynix already has DDR5-6400 in its sights which are built upon its second-generation 10nm class fabrication node. SK Hynix has now listed that it plans to develop up to DDR5-8400. Similar in methodology to its DDR5-6400 DRAM, DDR5-8400 requires much more forethought and application. What's interesting about SK Hynix's DDR5-8400 is the jump in memory banks, with DDR5-8400 using 32 banks, with 8 bank groups.
Not just content at increasing overall memory bandwidth and access performance over DDR4, the new DDR5 will run with an operating voltage of 1.1 V. This marks a 9% reduction versus DDR4's operating voltage which is designed to make DDR5 more power-efficient, with SK Hynix reporting that it aims to reduce power consumption per bandwidth by over 20% over DDR4.
To improve performance and increase reliability in server scenarios, DDR5-8400 will use on-die ECC (Error Correction) and ECS (Error Check and Scrub) which is a milestone in the production of DDR5. This is expected to reduce overall costs, with ECS recording any defects present and sends the error count to the host. This is designed to improve transparency with the aim of providing enhanced reliability and serviceability within a server system. Also integrated into the design of the DDR5-8400 DRAM is Decision Feedback Equalization (DFE), which is designed to eliminate reflective noise when running at high speeds. SK Hynix notes that this increases the speed per pin by a large amount.
In the above image from specification comparison between DDR4 and DDR5 from SK Hynix, one interesting thing to note is that it mentions DRAM chips with density up to 64 gigabit. We already know that the chip size of DDR5 is 65.22mm², with a data rate of 6.4 Gbps per pin, and uses its 1y-nm 4-metal DRAM manufacturing process. It is worth pointing out that the DDR5-5200 RDIMM we reported on back in November 18, uses 16 Gb DRAM chips, with further scope to 32 Gb reported. SK Hynix aims to double this to 64 Gb chips which do double the density, at lower power with 1.1 volts.
Head of DRAM Product Planning at SK Hynix, Sungsoo Ryu stated that:
"In the 4th Industrial Revolution, which is represented by 5G, autonomous vehicle, AI, augmented reality (AR), virtual reality (VR), big data, and other applications, DDR5 DRAM can be utilized for next-gen high-performance computing and AI-based data analysis".
SK Hynix if still on schedule with the current Coronavirus COVID-19 pandemic, looks set to enter mass production of DDR5 later this year.
Source: SK Hynix
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mode_13h - Friday, April 3, 2020 - linkUm...
> which allows the system the ability to use other banks while others are in use,
" to use other banks while one is refreshing," ?
> This is expected to reduce overall cost reduction,
" provide overall cost reduction," ?
> with ECS recording any defects present and counts the error count to the host.
" and sends the error count to the host." ?
name99 - Friday, April 3, 2020 - link"> which allows the system the ability to use other banks while others are in use"
Not JUST refreshing.
The fundamental unit of DDR4 was the 64-bit wide channel which, feeding an 8-beat burst, delivers up 64-bytes aka one cache line on most devices.
How do you double the number of beats while still retaining 64-byte cache lines?
By making the fundamental unit a 64-bit wide "physical" channel which is split into two 32-bit wide "logical" and independent channels. So even on a nominally single-channel device (ie something like a normal phone with just a single 64-bit connection to DRAM) both these channels can now operate simultaneously and independently.
Which means that, as much as possible, you'd like them to be hitting different "lower-level" structures (ie different banks) which can both simultaneously provide data.
Great_Scott - Friday, April 3, 2020 - linkAwesome performance! Shame that the overall latency is the same as DDR4... and DDR3... and DDR3...
mode_13h - Friday, April 3, 2020 - link> "In the 4th Industrial Revolution, which is represented by 5G, autonomous vehicle, AI, augmented reality (AR), virtual reality (VR), big data, and other applications, DDR5 DRAM can be utilized for next-gen high-performance computing and AI-based data analysis".
So, did this guy lose a bet, or is he just *really* trying to help anyone playing buzzword bingo? I don't recall the last time I saw so many packed into a single sentence!
drexnx - Friday, April 3, 2020 - linkI've heard a similar spiel from a totally different non-PC Tech source.
Same buzzwords, similar phrasing
ikjadoon - Friday, April 3, 2020 - linkTBF, faster & higher density DDR5 RAM really *is* needed for those advancements, honestly. I don't know how Startup.io is doing anything, but DDR5 is absolutely critical (e.g., sine qua non) for advancements in AR, VR GPUs, and AI / neural nets.
As always, industrial/enterprise/commercial drive the bleeding edge of the market. The consumer is the "2nd half" volume customer for new technologies.
mode_13h - Saturday, April 4, 2020 - linkYo, I get that DDR5 is a buzzword-enabling technology. That doesn't mean you have to sling them like a 6-shooter at the OK corral.
BTW, I think HBM2 is doing more to power AI. Especially training.
willis936 - Friday, April 3, 2020 - linkPretty cool about the DFE, though I'm surprised to learn it wasn't present in previous DDR generations. I know there must be some form of trained EQ, or else those data rates simply would not work in those channels. It appears that EQ has been outside the scope of the JEDEC spec, but vendors need to implement it. I think a lot would be gained in adding a side channel in the physical layer for handling these things. Especially when the BER is so stringent (1E-16 is not trivial to validate).
ksec - Friday, April 3, 2020 - linkMost consumer may not be excited by any of these but it surely is exciting for servers. We are already running into bandwidth wall for some application and High Density Memory is insanely expensive. Hopefully DDR5 fix both while bringing down TCO with lower energy usage.
Assuming everything is perfectly executed, AMD Zen 4 may hit a home run with PCI-E 5.0 and DDR 5.
rahvin - Friday, April 3, 2020 - linkAt best it'll be year before dimm's are available. i doubt Zen3 will support it. They have to design the support in years in advance. Zen4 maybe, but even that may be a long shot.