Intel Lists Knights Mill Xeon Phi on ARK: Up to 72 cores at 320W with QFMA and VNNIby Ian Cutress on December 19, 2017 7:00 AM EST
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- Xeon Phi
- Knights Mill
Today it was noticed, without any fanfare from Intel, that Knights Mill information has been uploaded to Intel’s specification database ARK. There are three known SKUs so far, with up to 72 cores and a 320W TDP. The Xeon Phi 'Knights Mill' products are a new iteration on the older 'Knights Landing' family, with a silicon change for additional AVX-512 instructions. As far as we can tell, these parts will only be available as socketable hosts and not as PCIe add-in cards.
In Intel’s approach to AI and compute and the data center, according to their talk at Hot Chips earlier this year, has multiple solutions depending on the workload. The Xeon Scalable Platform is meant for the widest variety of workloads, Xeon Phi for parallel acceleration and AI training, FPGAs for deep learning inference efficiency and the Crest family with dedicated deep learning by design. Each segment has its own roadmap, and the Xeon Phi roadmap has been somewhat confusing of late.
Moving from the 45nm Knights Ferry in 2010, Intel released 22nm Knights Corner in 2012 and 14nm Knights Landing in 2016. Last year, Intel had a contract with the Argonne National Laboratory to build the Aurora supercomputer at using 10nm Knights Hill (KNH) by 2020, which was the original successor to Knights Landing, however the KNH project was officially scrapped last month (Nov 2017) for various reasons, some citing Intel’s delay in releasing 10nm silicon. Intel still intends to follow through with the Aurora contract by 2021, it should be noted.
The new successor to Knights Landing (KNL) is Knights Mill (KNM), which was detailed back at Hot Chips. For the most part, the KNL and KNM chips are almost identical in core counts, frequencies, 36 PCIe 3.0 lanes, using 16GB of high-bandwidth MCDRAM and having six DRAM channels, but KNM offers a small design tweak to allow for better utilization of its AVX-512 units through supporting new sets of AVX-512 instructions as well as a small amount of silicon redesign. For pure performance metrics, this change means that Knights Mill offers only half of the double-precision performance of Knights Landing, but up to 2x in single precision and 4x with variable precision.
|Intel Xeon Phi x205 Family (Knights Mill)|
|7295||72 / 288||1.50 GHz||1.60 GHz||36 MB||320W||DDR4-2400||77ºC|
|7285||68 / 272||1.30 GHz||1.40 GHz||34 MB||250W||DDR4-2400||72ºC|
|7235||64 / 256||1.30 GHz||1.40 GHz||32 MB||250W||DDR4-2133||72ºC|
The three parts are officially members of the Xeon Phi x205 family, and match their x200 family members where the product numbers align (eg 7290 and 7295). The 7295 has the most cores and threads, with a higher frequency, more total L2 cache, support for DDR4-2400 and the higher temperature support. The 7285 is the middle of the pack, while the low end 7235 gives up some memory support, with only up to DDR4-2133.
The previous generation parts had some integrated OmniPath fabric versions (such as the 7290F) which do not seem to have migrated over to Knights Mill yet, though could potentially in the future. Each of the parts are similar to KNL, using 36 tiles of two cores, all connected with the 2D mesh, and each tile sharing 1MB of L2 cache with one VPU per core.
On the specification side, everything seems pretty much by the book for core counts and frequencies. The one number that stands out is the 320W for the Xeon Phi 7295. This is a high power consumption number for a socketed processor, and if my memory serves me correctly, this is the highest TDP ever assigned to an Intel socketed CPU. This isn't the highest for a socketed processor though - IBM quoted 300-350W for its z14 hardware earlier this year, although it can go up to 500W on consumer request. The reason for this dramatic increase in Intel’s TDP number (we suspect) is three-fold: one, to catch more processors off the production line into the relevant voltage/frequency window, and two, the new instructions offer better utilization of the silicon, and three: double-pumped execution.
|AVX-512 Support Propogation by Various Intel CPUs|
|Xeon, Core X||General||Xeon Phi|
|Source: Intel Architecture Instruction Set Extensions and Future Features Programming Reference (pages 12 and 13)|
The two headline changes on instructions for the new parts revolve around support for Quad FMA (QFMA, or 4FMAPS) for 32-bit floating point, and Vector Neural Network Instructions (VNNI) for 16-bit integers. To do this required changing the execution ports on the core.
Previously each VPU per core would offer identical 512-bit interfaces to the AVX-512 unit, supporting single precision (SP) and double precision (DP) math, with any half-precision (HP) falling under an SP block. In the new design, the ports are asymmetrical: the SP/DP block is split into a separate DP and SP/VNNI blocks, with one DP block removed (likely due to the size of the SP/VNNI block). This is best shown in the diagram above, though it means that DP performance is halved (2 blocks to 1), but SP performance is doubled (2 blocks to 4) and VNNI performance is quadrupled (2 SP blocks to 4 HP blocks).
The QFMA implementation allows for sequential fused-multiply-add to accumulate over four sets of calculations with a single instruction. Technically this adds latency, so the calculation needs enough ILP to hide the latency, but offers a single target for the vector accumulator and allows packing together of 12 aligned cycles in DRAM. Each FMA takes about 3 cycles.
For VNNI, the core takes two 16-bit integer inputs to give one 32-bit integer output for a horizontal dot product operation. The reason for using integer math here is two-fold: one, it enables 31-bits of INT prevision vs 24-bits of mantissa in FP, but also because IEEE standards are easier to implement in INT math.
Support for these new instructions and the silicon redesign means two things: one, the decoder potentially can work less, with more math being packed into a single instruction, but also caters to what Intel thought was a bottleneck in AVX-512 utilization: not enough codes were using all the AVX-512 unit all the time. This is designed to help increase utilization, and therefore would increase power consumption.
The other part of the equation is double pumping the AVX-512 unit, ensuring that the unit is fed at all times while reducing decode power.
Overall the KNM core is looks almost identical to the KNL core, aside from the VPU port changes. It still decodes 2-ops per cycle but gives out-of-order execution with 72-inflight micro-ops. To hide a lot of the latency, 4-way hyperthreading is enabled, hence why a 64-core part gives 256 threads.
Intel’s major partners already have Knights Mill available for customers, although list pricing is currently not in Intel's Price List. It’s interesting that the data being added to Intel’s ARK platform wasn’t accompanied by any announcement, and seems to be a low-key affair.
Source: Wikichip on Twitter, Intel ARK
Something we missed in our first look at the specifications. Over the older Knights Landing parts, the new Knights Mill parts also support Intel virtualization technologies, specifically VT-d, VT-x and EPT.
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Elstar - Tuesday, December 19, 2017 - linkDepends on the size of your data set. If your problem doesn't fit easily into the GPU's memory, then Xeon Phi starts to look very attractive.
p1esk - Tuesday, December 19, 2017 - linkIt seems to me that MCDRAM is supposed to play the role of high bandwidth memory (equivalent of GPU memory), and it's also 16GB, so I don't see how is it any more attractive in this regard.
mode_13h - Tuesday, December 19, 2017 - linkAgreed. For deep learning, you're practically limited by the amount of *fast* memory.
Not only that, but Nvidia's V100 has 3x the memory bandwidth.
HStewart - Tuesday, December 19, 2017 - linkI think the most interesting thing I read here is 4-way Hyperthreading. Typically in the past, Intel uses the Xeon and other lines of CPU to work on more functionality and I am curious when 4 way hyperthread will come to Xeon and then mainline Core processors.
HStewart - Tuesday, December 19, 2017 - linkOne thing in Intel document states "Fast Short REP MOV" - I search and found nothing on this - it for Ice Lake generation. I am very curious what they are talking - with my past experience in assembly programming and compile knowledge REP MOV is used quite frequently - also used internally in C instruction such as MemCpy
bruno.uy - Tuesday, December 19, 2017 - linkMaybe memcpy of small blocks has less overhead?
HStewart - Tuesday, December 19, 2017 - link"Maybe memcpy of small blocks has less overhead?"
Sounds logical. Possibly this is the mostly where compliers uses it - typically in only a small string of smaller contents when it used. Not in huge arrays.
I would think since this is use so much that it would be a major performance increase in applications.
Wilco1 - Tuesday, December 19, 2017 - linkSmall sizes is exactly where the microcode has the largest penalty. It's certainly feasible to reduce that penalty somewhat (recent CPUs already made the instructions less slow), but it is unlikely to ever run as fast as an AVX implementation. In any case you won't see a major performance increase since applications don't use REP MOV due to being so slow.
Elstar - Tuesday, December 19, 2017 - linkIntel has been incrementally improving the performance of "REP MOV" with each CPU generation. The "Fast Short REP MOV" flag is just another round of these hardware improvements that signals to programmers that they can use "REP MOV" in more places instead of C's "memcpy()" (which may or may not be optimized for the given CPU).
mode_13h - Tuesday, December 19, 2017 - linkThat's horrible advice.
Much better to optimize memcpy() for your platform than to hard-code inline assembly. Intel contributes optimizations to glibc and GCC, so just using memcpy() is probably your best bet. A lot of glibc's string functions have been optimized with vector instructions for quite a while, actually.