TSMC Symposium 2024
Although TSMC can't claim to be the first fab to use extreme UV (EUV) lithography – that title goes to Samsung – they do get to claim to be the largest. As a result, the company has developed significant experience with EUV over the years, allowing TSMC to refine how they use EUV tooling to both improve productivity/uptime, and to cut down on the costs of using the ultra-fine tools. As part of the company's European Technology Symposium this week, they went into a bit more detail on their EUV usage history, and their progress on further integrating EUV into future process nodes. When TSMC started making chips using EUV lithography in 2019 on its N7+ process (for Huawei's HiSilicon), it held 42% of the...
TSMC to Expand Specialty Capacity by 50%, Introduce 4nm N4e Low-Power Node
With all the new fabs being built in Germany and Japan, as well as the expansion of production capacity in China, TSMC is planning to extend its production capacity...
0 by Anton Shilov yesterday
TSMC Readies Next-Gen HBM4 Base Dies, Built on 12nm and 5nm Nodes
Of the several major changes coming with HBM4 memory, one of the most immediate is the sheer width of the memory interface. With the fourth-generation memory standard moving from...
1 by Anton Shilov yesterday
TSMC: Performance-Optimized 3nm N3P Process on Track for Mass Production This Year
As part of the second leg of TSMC's spring technology symposium series, the company offered an update on the state of its 3nm-class processes, both current and future. Building...
17 by Anton Shilov 2 days ago
TSMC Readies 8x Reticle Super Carrier Interposer For Next-Gen Chips Twice as Large As Today's
TSMC is no stranger to building big chips. Besides the ~800mm2 reticle limit of their normal logic processes, the company already produces even larger chips by fitting multiple dies...
6 by Anton Shilov on 4/30/2024
TSMC Jumps Into Silicon Photonics, Lays Out Roadmap For 12.8 Tbps COUPE On-Package Interconnect
Optical connectivity – and especially silicon photonics – is expected to become a crucial technology to enable connectivity for next-generation datacenters, particularly those designed HPC applications. With ever-increasing bandwidth...
9 by Anton Shilov on 4/26/2024
TSMC's System-on-Wafer Platform Goes 3D: CoW-SoW Stacks Up the Chips
TSMC has been offering its System-on-Wafer integration technology, InFO-SoW, since 2020. For now, only Cerebras and Tesla have developed wafer scale processor designs using it, as while they have...
2 by Anton Shilov on 4/26/2024
TSMC Preps Cheaper 4nm N4C Process For 2025, Aiming For 8.5% Cost Reduction
While the bulk of attention on TSMC is aimed at its leading-edge nodes, such as N3E and N2, loads of chips will continue to be made using more mature...
5 by Anton Shilov on 4/25/2024
TSMC 2nm Update: N2 In 2025, N2P Loses Backside Power, and NanoFlex Brings Optimal Cells
Taiwan Semiconductor Manufacturing Co. provided several important updates about its upcoming process technologies at its North American Technology Symposium 2024. At a high level, TSMC's 2 nm plans remain...
0 by Anton Shilov on 4/25/2024
TSMC's 1.6nm Technology Announced for Late 2026: A16 with "Super Power Rail" Backside Power
With the arrival of spring comes showers, flowers, and in the technology industry, TSMC's annual technology symposium series. With customers spread all around the world, the Taiwanese pure play...
18 by Anton Shilov on 4/25/2024
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