FOVEROS

One of the issues facing next-generation 3D stacking of chips is how to increase the density of the die-to-die interface. More connections means better data throughput, reducing latency and increasing bandwidth between two active areas of silicon that might be manufactured at different process nodes. There’s also a consideration for power and thermal hotspots as well. Intel has been developing its own physical interconnect topologies, most of which we’ve covered in detail before, such as the Embedded Multi-Die Interconnect Bridge (EMIB) that allows 2D expansion and Foveros die-to-die 3D staking that enables vertical expansion. As part of Intel’s Architecture Day 2020, we have a glimpse into Intel’s future with hybrid bonding. There are several holistic metrics to measure how ‘good’ an interconnect can be; the...

The Intel Lakefield Deep Dive: Everything To Know About the First x86 Hybrid CPU

For the past eighteen months, Intel has paraded its new ‘Lakefield’ processor design around the press and the public as a paragon of new processor innovation. Inside, Intel pairs...

225 by Dr. Ian Cutress on 7/2/2020

Intel Discloses Lakefield CPUs Specifications: 64 Execution Units, up to 3.0 GHz, 7 W

Over the past 12 months, Intel has slowly started to disclose information about its first hybrid x86 platform, Lakefield. This new processor combines one ‘big’ CPU core with four...

79 by Dr. Ian Cutress on 6/10/2020

Lenovo’s ThinkPad X1 Fold: Combining Foldable Displays, 5G and Lakefield into a… Laptop?

In 2019 we were exposed to the first foldable display smartphones and wearables, with the Samsung Galaxy Fold, Huawei Mate X, and Xiaomi Mi Mix all demonstrating various themes...

16 by Dr. Ian Cutress on 1/6/2020

An Interconnected Interview with Intel’s Ramune Nagisetty: A Future with Foveros

I’ve constantly stated for the last two years that the next battleground in performance for the semiconductor market is going to be in the interconnect – whether we’re speaking...

15 by Dr. Ian Cutress on 1/3/2020

Intel: Lakefield in 2020, Possible 5G on Foveros

At the IEEE International Electron Devices Meeting (IEDM) 2019, Intel had two package integration presentations, one on its Omni-Directional Interconnect and one on its 3D stacking Foveros technology. In...

37 by Dr. Ian Cutress on 12/11/2019

Intel’s Xe for HPC: Ponte Vecchio with Chiplets, EMIB, and Foveros on 7nm, Coming 2021

Today is Intel’s pre-SC19 HPC Devcon event, and with Raja Koduri on stage, the company has given a small glimpse into its high-performance compute accelerator strategy for 2021. Intel...

16 by Dr. Ian Cutress on 11/17/2019

Hot Chips 31 Live Blogs: Intel Lakefield and Foveros

One of the interesting developments in packaging technology in recent memory is the 3D stacking of Intel's new Foveros technology. The first chip to use this packaging technology is...

31 by Dr. Ian Cutress on 8/20/2019

Intel Details Manufacturing through 2023: 7nm, 7+, 7++, with Next Gen Packaging

At Intel's Investor Day today, CEO Bob Swan and Murthy Renduchintala spoke to the ability of the company with respect to its manufacturing capabilities. Intel has historically been strong...

237 by Ian Cutress & Anton Shilov on 5/8/2019

Intel's Interconnected Future: Combining Chiplets, EMIB, and Foveros

While Intel works on getting its main manufacturing process technology on track, it is spending just as much time and effort in researching and developing the rest of the...

117 by Ian Cutress on 4/17/2019

CES 2019 Quick Bytes: Intel’s 10nm Hybrid x86 Foveros Chip is Called Lakefield

At Intel’s Architecture Day, the company showed off a new stacking technology called ‘Foveros’, which is designed to allows the company to make smaller chips. The idea behind Foveros...

10 by Ian Cutress on 1/7/2019

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