EMIB

One of the issues facing next-generation 3D stacking of chips is how to increase the density of the die-to-die interface. More connections means better data throughput, reducing latency and increasing bandwidth between two active areas of silicon that might be manufactured at different process nodes. There’s also a consideration for power and thermal hotspots as well. Intel has been developing its own physical interconnect topologies, most of which we’ve covered in detail before, such as the Embedded Multi-Die Interconnect Bridge (EMIB) that allows 2D expansion and Foveros die-to-die 3D staking that enables vertical expansion. As part of Intel’s Architecture Day 2020, we have a glimpse into Intel’s future with hybrid bonding. There are several holistic metrics to measure how ‘good’ an interconnect can be; the...

An Interconnected Interview with Intel’s Ramune Nagisetty: A Future with Foveros

I’ve constantly stated for the last two years that the next battleground in performance for the semiconductor market is going to be in the interconnect – whether we’re speaking...

15 by Dr. Ian Cutress on 1/3/2020

Intel’s Xe for HPC: Ponte Vecchio with Chiplets, EMIB, and Foveros on 7nm, Coming 2021

Today is Intel’s pre-SC19 HPC Devcon event, and with Raja Koduri on stage, the company has given a small glimpse into its high-performance compute accelerator strategy for 2021. Intel...

16 by Dr. Ian Cutress on 11/17/2019

Intel’s EMIB Now Between Two High TDP Die: The New Stratix 10 GX 10M FPGA

The best thing about manufacturing Field Programmable Gate Arrays (FPGAs) is that you can make the silicon very big. The nature of the repeatable unit design can absorb issues...

31 by Dr. Ian Cutress on 11/5/2019

Intel Details Manufacturing through 2023: 7nm, 7+, 7++, with Next Gen Packaging

At Intel's Investor Day today, CEO Bob Swan and Murthy Renduchintala spoke to the ability of the company with respect to its manufacturing capabilities. Intel has historically been strong...

237 by Ian Cutress & Anton Shilov on 5/8/2019

Intel's Interconnected Future: Combining Chiplets, EMIB, and Foveros

While Intel works on getting its main manufacturing process technology on track, it is spending just as much time and effort in researching and developing the rest of the...

117 by Ian Cutress on 4/17/2019

Intel Provides Royalty-Free License for Data Bus to DARPA’s Modular Chips Initiative

Taking place this week is DARPA’s 2018 Electronic Resurgence Initiative (ERI) Summit, the defense research agency's first gathering to address the direction of US technology manufacturing as Moore's Law...

14 by Anton Shilov on 7/25/2018

Intel Launches Stratix 10 TX: Leveraging EMIB with 58G Transceivers

One of the key takeaways from Hot Chips last year was that Intel’s EMIB strategy was going to be fixed primarily in FPGAs to begin with. Intel instigated a...

7 by Ian Cutress on 2/26/2018

The AnandTech Podcast, Episode 42: Intel with Radeon Graphics

Every so often, the technology industry goes crazy. To get three events along those lines in the same week just blows the mind. On this podcast, Ian and Ryan...

9 by Ian Cutress on 11/13/2017

Intel to Create new 8th Generation CPUs with AMD Radeon Graphics with HBM2 using EMIB

Today Intel (and AMD) are announcing a partnership to create processors using Intel's high-performance x86 cores, AMD Radeon Graphics, and HBM2 within a single processor package using Intel's latest...

254 by Ian Cutress on 11/6/2017

Intel Displays 10nm Wafer, Commits to 10nm ‘Falcon Mesa’ FPGAs

On the back of Intel’s Technology and Manufacturing Day in March, the company presented another iteration of the information at an equivalent event in Beijing this week. Most of...

52 by Ian Cutress on 9/19/2017

Hot Chips: Intel EMIB and 14nm Stratix 10 FPGA Live Blog (8:45am PT, 3:45pm UTC)

Today at Hot Chips we have a lot of interesting talks going on. First up is a talk on Intel's latest 14nm FPGA solution: Stratix 10 implementing HBM using...

51 by Ian Cutress on 8/22/2017

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