When AMD started using TSMC’s 7nm process for the Zen 2 processor family that launched in November 2019, one of the overriding messages of that launch was that it was important to be on the leading edge of process node technology to be competitive. That move to TSMC N7 was aided by the small chiplets used in the desktop processors at the time, ensuring a higher yield and better binning curves for desktop and enterprise processors. However, between now and then, we’ve seen other companies take advantage of TSMC’s 5nm, 4nm, and talk about TSMC’s 3nm process coming to market over the next 12-24 months. During our roundtable discussion with CEO Dr. Lisa Su, I asked if the need to stay on the leading edge still held true.

To put this into perspective, AMD announced late in 2021 that it would be using TSMC’s 5nm process for its Zen 4 chiplets in enterprise CPUs in the second half of 2022. Then in early 2022, the company reiterated the use of Zen 4 chiplets, but this time in desktop processors again by the end of 2022. This is a significant delay between the first use of TSMC 5nm by the smartphone vendors, which reached mass production in Q3 2020, with Apple and Huawei being the first to take advantage. Even today, if we go beyond 5nm, Mediatek has already announced that its upcoming Dimensity 9000 smartphone chip is on TSMC 4nm and will come to market earlier this year. TSMC’s 3nm process is expected to ramp production at the end of 2022, for a consumer launch in early 2023. By those metrics, AMD is behind a process node or two by the time Zen 4 chiplets come to market later this year.

I asked Dr. Su in our roundtable about whether the need to be on the leading edge process is critical to be competitive for them. Having innovated around chiplets, I asked whether being the lead partner with foundry partners and packaging partners (known as OSATs) is of major importance, especially when the lead competition seem ready to throw money at TSMC to take that volume. How would AMD be able to aggressively assert a market-leading position in light of the complexity of manufacturing and the financial power of the competition?

Dr. Su stated that AMD is continuing to innovate in all areas. For AMD it seems, leading the chiplet technology has helped to bring the package together. She went on to say that AMD has had strong delivery of 7nm, is introducing 6nm, followed by Zen 4 and 5nm, talking about 2D chiplets and 3D chiplets – AMD has all these things in the tool chest and are using the right technology for the right application. Dr Su reinforced that technology roadmaps are all about making the right choices and the right junctures, and explicitly stated that our 5nm technology is highly optimized for high-performance computing – it’s not necessarily the same as some other 5nm technologies out there.

While not explicitly stating that the need to be leading edge is no longer critical, this messaging follows the enhanced narrative from AMD that in the era of chiplets, it’s how they’re combined and packaged that is becoming important, arguably more important than exactly what process node is being used. We’ve seen this messaging before from AMD’s main competitor Intel, where back in 2017 the company stated that it will heavily rely on optimized chiplets for each use case – this was crystallized further in 2020 suggesting 24-36 chiplets on a single consumer desktop processor for purpose-built client designs. That being said, it has been constantly rumored that Intel will be a big customer of TSMC 3nm in the following years, so it will be interesting to see where AMD can take advantage of several years of chiplet expertise and packaging tools by comparison.

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  • nandnandnand - Monday, January 10, 2022 - link

    N4X is definitely considered a 5nm-class node and that might be what AMD is using here.

    The rumor that AMD would be using a better version of 5nm for Zen 4 has been floating around since April 2020:

  • dotjaz - Tuesday, January 11, 2022 - link

    Why do you people keep making stuff up? It's not N4X, it can never be N4X. First of all, Lisa Su explicitly said 5nm, not 5nm-class, otherwise there's no 6nm just 7nm. Secondly it takes at least two years from announcing a node to mass production, that'll be end of 2023 at best for N4X.
  • dotjaz - Tuesday, January 11, 2022 - link

    Also AMD have always been using a better or rather HPC optimised process. AMD never used vanilla N7 or N7P. TSMC referred to Zen2 process as N7 "large die" despite Zen2 being much smaller than A12X/A13. Microsoft referred to the improved version as N7e.
    You are the same kind of people who believed 7nm+ is N7+, when it's in fact just N7e based on enhanced N7P.
  • dotjaz - Tuesday, January 11, 2022 - link

    AMD will eventually use N4X with enhancements, likely in 2024 or later. But never the plain version.
  • FreckledTrout - Monday, January 10, 2022 - link

    No they wont. The N4X node isn't even in risk production as of yet. AMD will for sure be using N5 however it could be tweaked a bit for say fin pitch etc just for AMD.

    However could AMD have a Zen4 refresh of sorts like Zen+? Sure.
  • scineram - Tuesday, January 11, 2022 - link

    Zen 5 is more likely for that N4X node me thinks.
  • whatthe123 - Monday, January 10, 2022 - link

    they're expecting something like 2024 for N4X so that makes no sense at all. if they were using N4X they would say N4X as it would be considerably better than N5, and it's not like intel can magically materialize a better node if AMD were to announce N4X chips.
  • ikjadoon - Monday, January 10, 2022 - link

    > expect the first N4X designs to hit the market in early 2024

    Oh, yes. That’s it. The last paragraph in the N4X article nailed it.

    Thank you for the correction.
  • Jon Tseng - Tuesday, January 11, 2022 - link

    Hey, IIRC "high performance computing" is the term TSMC uses for flavours of its process which go into PC, server, GPU (i.e. fast boxes which plug into a wall). Usually used in contrast to LP or low power variants which is what goes into smartphones.

    So its different from the traditional usage of HPC in a supercomputing (e.g. Top500 context). Bit confusing I know but don't read too much into it!
  • dotjaz - Tuesday, January 11, 2022 - link

    Exactly, TSMC referred to those in various slides as N7 "large die", N5 HPC etc. "Large die" was Zen2 ironically smaller than A12/12X/13.

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