A Hybrid/Heterogeneous Design

Developing a processor with two different types of core is not a new concept – there are billions of smartphones that have exactly that inside them, running Android or iOS, as well as IoT and embedded systems. We’ve also seen it on Windows, cropping up on Qualcomm’s Windows on Snapdragon mobile notebooks, as well as Intel’s previous Lakefield design. Lakefield was the first x86 hybrid design in that context, and Alder Lake is the more mass-market realization of that plan.

A processor with two different types of core disrupts the typical view of how we might assume a computer works. At the basic level, it has been taught that a modern machine is consistent – every CPU has the same performance, processes the same data at the same rate, has the same latency to memory, the same latency to each other, and everything is equal. This is a straightforward homogenous design that’s very easy to write software for.

Once we start considering that not every core has the same latency to memory, moving up to a situation where there are different aspects of a chip that do different things at different speeds and efficiencies, now we move into a heterogeneous design scenario. In this instance, it becomes more complex to understand what resources are available, and how to use them in the best light. Obviously, it makes sense to make it all transparent to the user.

With Intel’s Alder Lake, we have two types of cores: high performance/P-cores, built on the Golden Cove microarchitecture, and high efficiency/E-cores, built on the Gracemont microarchitecture. Each of these cores are designed for different optimization points – P-cores have a super-wide performance window and go for peak performance, while E-cores focus on saving power at half the frequency, or lower, where the P-core might be inefficient.

This means that if there is a background task waiting on data, or something that isn’t latency-sensitive, it can work on the E-cores in the background and save power. When a user needs speed and power, the system can load up the P-cores with work so it can finish the fastest. Alternatively, if a workload is more throughput sensitive than latency-sensitive, it can be split across both P-cores and E-cores for peak throughput.

For performance, Intel lists a single P-core as ~19% better than a core in Rocket Lake 11th Gen, while a single E-core can offer better performance than a Comet Lake 10th Gen core. Efficiency is similarly aimed to be competitive, with Intel saying a Core i9-12900K with all 16C/24T running at a fixed 65 W will equal its previous generation Core i9-11900K 8C/16T flagship at 250 W. A lot of that will be that having more cores at a lower frequency is more efficient than a few cores at peak frequency (as we see in GPUs), however an effective 4x performance per watt improvement requires deeper investigation in our review.

As a result, the P-cores and E-cores look very different. A deeper explanation can be found in our Alder Lake microarchitecture deep dive, but the E-cores end up being much smaller, such that four of them are roughly in the same area as a single P-core. This creates an interesting dynamic, as Intel highlighted back at its Architecture Day: A single P-core provides the best latency-sensitive performance, but a group of E-cores would beat a P-core in performance per watt, arguably at the same performance level.

However, one big question in all of this is how these workloads end up on the right cores in the first place? Enter Thread Director (more on the next page).

A Word on L1, L2, and L3 Cache

Users with an astute eye will notice that Intel’s diagrams relating to core counts and cache amounts are representations, and some of the numbers on a deeper inspection need some explanation.

For the cores, the processor design is physically split into 10 segments.

A segment contains either a P-core or a set of four E-cores, due to their relative size and functionality. Each P-core has 1.25 MiB of private L2 cache, which a group of four E-cores has 2 MiB of shared L2 cache.

This is backed by a large shared L3 cache, totaling 30 MiB. Intel’s diagram shows that there are 10 LLC segments which should mean 3.0 MiB each, right? However, moving from Core i9 to Core i7, we only lose one segment (one group of four E-cores), so how come 5.0 MiB is lost from the total L3? Looking at the processor tables makes less sense.

 

Please note that the following is conjecture; we're awaiting confirmation from Intel that this is indeed the case.

It’s because there are more than 10 LLC slices – there’s actually 12 of them, and they’re each 2.5 MiB.  It’s likely that either each group of E-cores has two slices each, or there are extra ring stops for more cache.

Each of the P-cores has a 2.5 MiB slice of L3 cache, with eight cores making 20 MiB of the total. This leaves 10 MiB between two groups of four E-cores, suggesting that either each group has 5.0 MiB of L3 cache split into two 2.5 MiB slices, or there are two extra LLC slices on Intel’s interconnect.

Alder Lake Cache
AnandTech Cores
P+E/T
L2
Cache
L3
Cache
IGP Base
W
Turbo
W
Price
$1ku
i9-12900K 8+8/24 8x1.25
2x2.00
30 770 125 241 $589
i9-12900KF 8+8/24 8x1.25
2x2.00
30 - 125 241 $564
i7-12700K 8+4/20 8x1.25
1x2.00
25 770 125 190 $409
i7-12700KF 8+4/20 8x1.25
1x2.00
25 - 125 190 $384
i5-12600K 6+4/20 6x1.25
1x2.00
20 770 125 150 $289
i5-12600KF 6+4/20 6.125
1x200
20 - 125 150 $264

This is important because moving from Core i9 to Core i7, we lose 4xE-cores, but also lose 5.0 MiB of L3 cache, making 25 MiB as listed in the table. Then from Core i7 to Core i5, two P-cores are lost, totaling another 5.0 MiB of L3 cache, going down to 20 MiB. So while Intel’s diagram shows 10 distinct core/LLC segments, there are actually 12. I suspect that if both sets of E-cores are disabled, so we end up with a processor with eight P-cores, 20 MiB of L3 cache will be shown.

 
Intel Announces 12th Gen Core Alder Lake Thread Director: Windows 11 Does It Best
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  • kwohlt - Friday, October 29, 2021 - link

    "...just so Alder Lake can be supported better."
    Windows 11 aggressive cut-off is based on a lot of things, such as VBS support, Spectre-Meltdown hardware mitigations, etc. It's not due to accommodating Alder Lake whatsoever.
  • GeoffreyA - Friday, October 29, 2021 - link

    It is nonsense but more related to trying to push increased security in an arbitrary way. Truth is, W11 runs happily on a Pentium 4. Microsoft, the cat is out of the bag that the requirements are a sham.

    Anyhow, I suspect W11's coming out in quite a rough state was due to Alder Lake's release.
  • Oxford Guy - Friday, October 29, 2021 - link

    If MS continues to copy Apple it will implement hard locks to prevent it from running on anything but its arbitrary list.

    People should consider the incrementalist implications of MS’ radical change from being the OS of long-term hardware compatibility to being Apple Jr.
  • GeoffreyA - Saturday, October 30, 2021 - link

    Let's hope they don't follow in Apple's footsteps. Microsoft has a history of relenting when their choices haven't been sober. I understand they're trying to push increased, military-grade security; but when you're cutting out 90% of the world's computers, it doesn't seem sensible. As in life, moderation is best. W11 doesn't have a purpose, and though I haven't used it yet, reminds me of ME. It hasn't reached critical mass of change to warrant a departure from 10, which works flawlessly, and whose minimal approach fades away into the background, much like XP's did.

    As for your sentiment touching on consumer passiveness, you're right. If people got together and boycotted these tech products, when they're bad, companies will have to give in. Unfortunately, we just accept rubbish from them, and they get away with worse and worse. Turning the tables round, the famed entitlement of consumers also deserves some comment.
  • Oxford Guy - Sunday, October 31, 2021 - link

    'Turning the tables round, the famed entitlement of consumers also deserves some comment.'

    What entitlement?

    Have you shopped at a WalMart recently? One goes into the store, no one is available to check you out. When the machine (which was filthy — to the point where the attendant doesn't even know where the spray bottle is) goes haywire, the attendant comes over and wasted a great deal more of your time trying to get the broken computer to work. The attendant argues with you about the problem you can see with your own eyes and proceeds to overcharge you. If you have a problem with that you'll have to come to the store again when a manager is willing to be at the front area.

    That doesn't go into the big Orwellian televisions on every self-scan in some stores, the managers who lie to your face about product pricing and disappear as soon as you try to check out the alleged sale items, and people who are tasked with blocking your exit and making harassing comments.

    WalMart has been forced on consumers and it is leading the way in anti-entitlement.

    The now-legendary passivity in 'geek' tech is to be seen in the passivity concerning all of these degradations of the shopping experience.
  • GeoffreyA - Sunday, October 31, 2021 - link

    I don't even know where to start, and agree the shopping experience is anything but ideal. Not being very fond of shopping myself, I try to limit how much I go into the shops. I would say, all customers want is good service, friendliness, honouring what prices are listed, etc.

    Here in South Africa, Game and Makro are our Walmart analogues, and we've still got cashiers at the tills. Incidentally, Walmart acquired a majority stake in Massmart, the company that owns all these shops.
  • Oxford Guy - Thursday, October 28, 2021 - link

    'Perhaps it’s time for some new words.'

    Shakespeare coined many.
  • Oxford Guy - Thursday, October 28, 2021 - link

    Perhaps I didn't read carefully enough but I didn't see anything about ECC in the DRAM section. I saw a bunch of complex new tech for RAM (turbo and such).

    Maybe it's strange to think that prioritizing data safety should come before these other things.
  • mode_13h - Friday, October 29, 2021 - link

    Why would they mention ECC? This is a consumer CPU. Intel consumer CPUs generally don't support ECC memory, with but a few exceptions (i3's usually do, and select other low-end SKUs over the years).

    The Xeon E-series equivalent will almost surely support ECC memory*.

    * DDR5 supports internal ECC, but the datapath still doesn't have ECC bits by default, since that requires additional motherboard traces which translates into precious $0.001's (sarcasm).
  • Oxford Guy - Friday, October 29, 2021 - link

    ‘Why would they mention ECC? This is a consumer CPU.’

    Agreed. Consumers don’t have much use for RAM that reduces data loss/corruption. They need new stuff like turbo in their RAM. Priorities.

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