Intel Architecture Day 2021: Alder Lake, Golden Cove, and Gracemont Detailed
by Dr. Ian Cutress & Andrei Frumusanu on August 19, 2021 9:00 AM ESTGracemont Microarchitecture (E-Core) Examined
The smaller core as part of Intel’s hybrid Alder Lake design is called an E-core, and is built on the Gracemont microarchitecture. It forms part of Intel’s Atom family of processors, and is a significant microarchitectural jump over the previous Atom core design called Tremont.
- 2008: Bonnell
- 2011: Saltwell
- 2013: Silvermont
- 2015: Airmont
- 2016: Goldmont
- 2017: Goldmont Plus
- 2020: Tremont
- 2021: Gracemont
Based on Intel’s diagrams, the company is pitching that the size of its Golden Cove core means that in the space it would normally fit one of its P-core designs, it can enable a four core cluster of E-cores along with a shared 4MB L2 cache between them.
For performance, Intel has some pretty wild claims. It splits them up into single thread and multi-thread comparisons using SPECrate2017_int.
When comparing 1C1T of Gracemont against 1C1T of Skylake, Intel’s numbers suggest:
- +40% performance at iso-power (using a middling frequency)
- 40% less power* at iso-performance (peak Skylake performance)
*'<40%' is now stood to mean 'below 40 power'
When comparing 4C4T of Gracemont against 2C4T of Skylake, Intel’s numbers suggest:
- +80% performance peak vs peak
- 80% less power at iso performance)peak Skylake performance
We pushed the two Intel slides together to show how they presented this data.
By these graphics it looks like that for peak single thread, we should see around +8% better than Skylake performance while consuming just over half the power – look for Cinebench R20 scores for one Gracemont thread around 478 then (Skylake 6700K scored 443). With +8% for single thread in mind, the +80% in MT comparing 4 cores of Gracemont to two fully loaded Skylake cores seems a little low – we’ve got double the physical cores with Gracemont compared to Skylake here. But there’s likely some additional performance regression with the cache structure on the new Atom core, which we’ll get to later on this page.
These claims are substantial. Intel hasn’t compared the new Atom core generation on generation, because it felt that having AVX2 support would put the new Atom at a significant advantage. But what Intel is saying with these graphs is that we should expect better-than Skylake performance at much less power. We saw Skylake processors up to 28 cores in HEDT – it makes me wonder if Intel might not enable its new Atom core for that market. If that’s the case, where is our 64-core Atom version for HEDT? I’ll take one.
Front End
The big item about the Tremont front end of the core was the move to dual three-wide decode paths, enabling two concurrent streams of decode that could support 3 per cycle. That still remains in Gracemont, but is backed by a double-size 64 KB L1 Instruction cache. This ties into the branch predictor which enables prefetchers at all cache levels, along with a 5000-entry branch target cache which Intel says in improved over the previous generation.
Back on the decoder, Intel supports on-demand decode which stores a history of previous decodes in the instruction cache and if recent misses are recalled at the decode stage, the on-demand stream will pull directly from the instruction cache instead, saving time – if the prefetch/decode works, the content in the instruction cache is updated, however if it is doing poorly then the scope is ‘re-enabled for general fetches’ to get a better understanding of the instruction flow. This almost sounds like a micro-op cache without having a physical cache, but is more to do about instruction streaming. Either way, the decoders can push up to six uops into the second half of the front end.
For Gracemont, the reorder buffer size has increased from 208 in Tremont to 256, which is important aspect given that Gracemont now has a total of 17 (!) execution ports, compared to eight in Tremont. This is also significantly wider than the execution capabilities of Golden Cove's 12 ports, related to the disaggregated integer and FP/vector pipeline design. However, despite that width, the allocation stage feeding into the reservation stations can only process five instructions per cycle. On the return path, each core can retire eight instructions per cycle.
Back End
So it’s a bit insane to have 17 execution ports here. There are a lot of repeated units as well, which means that Gracemont is expecting to see repeated instruction use and requires the parallelism to do more per cycle and then perhaps sit idle waiting for the next instructions to come down the pipe. Overall we have
- 4 Integer ALUs (ALU/Shift), two of which can do MUL/DIV
- 4 Address Generator Units, 2 Load + 2 Store
- 2 Branch Ports
- 2 Extra Integer Store ports
- 2 Floating Point/Vector store ports
- 3 Floating Point/Vector ALUs: 3x ALUs, 2x AES/FMUL/FADD, 1x SHA/IMUL/FDIV
It will be interesting to see exactly how many of these can be accessed simultaneously. In previous core designs a lot of this functionality would be enabled though the same port – even Alder Lake’s P-core only has 12 execution ports, with some ports doing double duty on Vector and Integer workloads. In the P-core there is a single scheduler for both types of workloads, whereas in the E-core there are two separate schedulers, which is more akin to what we see on non-x86 core designs. It’s a tradeoff in complexity and ease-of-use.
The back-end is support by a 32 KiB L1-Data cache, which supports a 3-cycle pointer chasing latency and 64 outstanding cache misses. There are two load and two store ports, which means 2x16 byte loads and 2 x 16 byte stores to the L1-D.
There is also has a shared 4 MB L2 cache across all four E-cores in a cluster with 17-cycle latency. The shared L2 cache can support 64 bytes per cycle read/write per core, which Intel states is sufficient for all four cores. The new L2 supports up to 64 outstanding misses to the deeper memory subsystem – which seems fair, but has to be shared amongst the 4 cores.
Intel states that it has a Resource Director that will arbitrate cache accesses between the four cores in a cluster to ensure fairness, confirming that Intel are building these E-cores in for multi-threaded performance rather than latency sensitive scenarios where one thread might have priority.
Other Highlights
As the first Atom core to have AVX2 enabled, there are two vector ports that support FMUL and FADD (port 20 and port 21), which means that we should expect peak performance compared to previous Atoms to be substantial. The addition of VNNI-INT8 over the AVX unit means that Intel wants these E-cores to enable situations where high inference throughput is needed, such as perhaps video analysis.
Intel was keen to point out that Gracemont has all of its latest security features including Control Flow Enhancement Technology (CET), and virtualization redirects under its VT-rp feature.
Overall, Intel stated that the E-cores are tuned for voltage more than anything else (such as performance, area). This means that the E-cores are set to use a lot less power, which may help in mobile scenarios. But as mentioned before on the first page, it will depend on how much power the ring has to consume in that environment - it should be worth noting that each four core Atom cluster only has a single stop on the full ring in Alder Lake, which Intel says should not cause congestion but it is a possibility – if each core is fully loaded, there is only 512 KB of L2 cache per core before making the jump to main memory, which indicates that in a fully loaded scenario, that might be a bottleneck.
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Gondalf - Thursday, August 19, 2021 - link
You mean 5nm Zen 4 will have AVX512.Anyway wait and see if only on server cores or even in consumer, sure 5nm will give room for AVX512 in desktop cpus, but it is not for certain.
The funny thing we are in front of a tight situation for both Intel and AMD.
AMD can not go seriously on 5nm because there are not enough wafers around, Intel have to wait 7nm for new designs.
Intersting times, if roadmaps are true, both AMD and Intel will are on a 5nm class process around at the same time, sometime at the end of 2022.
We'll see the best one between two contenders.
JayNor - Thursday, August 19, 2021 - link
Looks like a Sapphire Rapids HEDT would be Intel's solution for pro consumers who want avx512. It would include bfloat16 support and AMX tiled matrix operations, which have not been available previously.An eight core Golden Cove HEDT chip with its dual avx512 and tiled matrix bfloat16 units enabled sounds like a decent upgrade from Ice Lake HEDT.
mode_13h - Friday, August 20, 2021 - link
Does SPR have BFloat16 in AVX-512, or just via AMX? I thought its AVX-512 is still not fully caught up with Cooper Lake.Kamen Rider Blade - Thursday, August 19, 2021 - link
The desktop processor will have sixteen lanes of PCIe 5.0, which we expect to be split as x16 for graphics or as x8 for graphics and x4/x4 for storage. This will enable a full 64 GB/s bandwidth. Above and beyond this are another four PCIe 4.0 lanes for more storage. As PCIe 5.0 NVMe drives come to market, users may have to decide if they want the full PCIe 5.0 to the discrete graphics card or notWhy won't they allow BiFurication of PCIe 5.0 = x12 + x4 as an option?
x12 PCIe lanes is part of the PCIe spec, it should be better supported.
Same with PCIe Gen 5.0 x12 + x2 + x2
That can offer alot of flexibility in end user setups.
mode_13h - Friday, August 20, 2021 - link
The reality is that consumers don't need PCIe 5.0 x16. The benefits of even 4.0 x16 are small (but certainly real, in several cases).IMO, the best case for PCIe 5.0 would be x8 + x8 for multi-GPU setups. This lets you run dual-GPU, with each getting the same bandwidth as if it had a 4.0 x16 link.
Unfortunately, they seem to have overlooked that obvious win, and all for the sake of supporting a use case we certainly won't see within the life of this platform: a SSD that can actually exceed 4.0 x4 speeds.
Dug - Friday, August 20, 2021 - link
As long as I can have 3 ssd's that can run full speed at PCIe 4.0, I'll be happy.mode_13h - Thursday, August 19, 2021 - link
The Thread Director is intriguing. I wonder how much of the same information can be gleaned from the performance counter registers, although having an embedded microcontroller analyze it saves the OS from the chore of doing so.Can it raise interrupts, though? If not, then I don't see much point to enabling performance characterization in 30 microseconds, as that's way shorter than an OS timeslice.
It should be an interesting target for new sidechannel attacks, as well.
Jorgp2 - Thursday, August 19, 2021 - link
Isn't it hardware feedback interface, not hardware frequency interface?eastcoast_pete - Thursday, August 19, 2021 - link
To me, the star of the CPU cores is the "little" one, Gracemont. Question about AL in Ultrabooks: Why not an SoC with 4, 6, or 8 Gracemont cores plus some Xe Graphics, at least for the lower end? For most regular business use cases, that'll do just fine. The addition of AVX/AVX2 also means that certain effects for video conferencing, such as virtual backgrounds (Teams, other) is now possible with these beefed-up Atoms.And, on the other end of the spectrum, I agree with Ian that a 32 or more Gracemont-core CPU would work well if you want to run a lot of threads within a reasonable power envelope. @Ian: any chance you can get your hands on one of the CPUs specified for 5G base stations? Even the current, Tremont-based ones are exactly that: many Atom cores in one, specialized server CPU. Would be nice to see how those go.
eastcoast_pete - Thursday, August 19, 2021 - link
To be very precise: I meant an SoC without any "Cove" cores, just 4 or more Gracemonts. It'll do for many, especially business uses.