So far we have three products in the market built on TSMC’s N5 process: the Huawei Kirin 9000 5G SoC, found in the Mate 40 Pro, the Apple A14 SoC, found in the iPhone 12 family, and the Apple M1 SoC, which is in the new MBA/MBP and Mac Mini. We can now add another to that list, but it’s not a standard SoC: here we have IP for a SerDes connection, now validated and ready for licensing in TSMC N5. Today Marvell is announcing its DSP-based 112G SerDes solution for licensing.

Modern chip-to-chip networking infrastructure relies on high speed SerDes connections to enable a variety of different protocols at a range of speeds, typically in Ethernet, fiber optics, storage, and connectivity fabrics. Current high-speed connections rely on 56G connections, and so moving up to 112G enables double the speed. Several companies have 112G IP available, however Marvell is the first to enable it in 5nm, ensure it is hardware validated, and offer it for licensing.

These sorts of connections have a number of measurements to compare them to other 112G solutions: the goal is to not only meet the standard, but offer a solution that uses less power, but also a lower potential error rate, especially for high-speed high-reliability infrastructure applications. Marvell is claiming that its new solution enables a significant power reduction in energy per bit transferred – up to 25% compared to equivalent TSMC 7nm offerings, along with tight power/thermal constraints and a >40dB insertion loss.

We typically expect data to travel down a connection like this as a series of ones and zeros, i.e. a 1-bit operation which can be a 0 or a 1, known as NRZ (non-return to zero) - however Marvell’s solution enables 2-bit operation, such as a 00, 01, 10, or 11, known as PAM4 (Pulse Amplitude Modulation). This enables double the bandwidth, but does require some extra circuitry. PAM4 has been enabled at lower SerDes speeds and at 112G before, but not for TSMC N5. As we move to even faster speeds, PAM4 will become a necessity to enable them. Regular readers may identify that NVIDIA’s RTX 3090 uses PAM4 signaling (on N7) to enable over 1000 GB/s of bandwidth with Micron’s GDDR6X – it can also be run in NRZ mode for lower power if needed.


Image from Micron

Marvell says it is already engaged with its custom ASIC customers across multiple markets with the 112G implementation. Alongside the new 112G SerDes, the company says it is set to enable a complete suite of PHYs, switches, DPUs, custom processors, controllers, and accelerators built on 5nm, and that this initial offering is but the first step.

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  • Ditiris - Wednesday, November 18, 2020 - link

    Pretty sure the time interval on that eye diagram should be 125 ps, not 125 ns. Reply
  • Brane2 - Thursday, November 19, 2020 - link

    Your graph is crap.
    If the timing was 125ns, you'd be looking at something from Atari ST/AMiga era.
    It's more likely 125 ps.
    But what's a mere 1000x between friends ?
    Reply
  • Spunjji - Thursday, November 19, 2020 - link

    It's not their "graph", it's Micron's. Take it up with them. Reply
  • TimSyd - Saturday, November 21, 2020 - link

    "Regular readers may identify that NVIDIA’s RTX 3090 uses PAM4 signaling (on N7) to enable over 1000 GB/s of bandwidth with Micron’s GDDR6X"

    The RTX 3000 series are all on Samsung 08 not TSMC N7, though Nvidia probably regrets that now ;)
    Reply
  • ucwby - Monday, November 23, 2020 - link

    I've been designing chips with PAM4 for 5+ years. It's nothing new. It's nice to see more SERDES options to help break the BRCM monopoly on this. This one critical IP is why BRCM retains a lot of their ASIC customers and charges their extortionist rates. Still, it would take a incredibly brave silicon design team to roll the dice MRVL. Every cutting edge SERDES looks great on paper but falls way short when tape-out comes. Wipe that smug smile off your face BRCM. Reply

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