Santoval. considering zen 2 looks to be on par, or slightly faster then intel at the clocks they are at... why would they need to be higher ? do you want amd to make intel look worse ? :-)
notashill " And the base is 300Mhz higher which I absolutely believe would increase power draw by 50%, it is simply going way past the efficiency sweet spot of the chip. Very much in line with my experience overclocking the current Ryzen chips. " oh?? 300 mhz = 50% more power ??? would you have a source for this ? also.. Zen 2, is not current ryzen chips.. untill Zen 2 is released, and are reviewed, and in the hands of the public, how Zen 2 overclocks.. is still a mystery...
Just from my own testing on a 1700, 3.7Ghz all core is about 100W and 4.0 is about 150 and pushing the safe voltage limits. IIRC anandtech's various Ryzen reviews had some good power measurements with overclocking data.
Of course 7nm may result in wildly different voltage/power/freq scaling so who knows until the new chips are in the wild to test.
Linus Tech Tips has a pretty interesting take on all this via their youtube video that's trending up with nearly a million views and 6000 comments in the last 12 hours. I don't doubt for a moment that Ian here has a lot to say about all this stuff as well. Look forward to hearing his thoughts. You guys must be just swamped at Anand over all this. Hopefully pumped to. I have not seen this sort of buzz in quite some time.
Not sure what else they could drop that wouldn't be underwhelming in comparison to what was released over the last 24hrs. Biggest news day for Amd in over a decade.
It isn’t NUMA. The original Ryzen processors were not NUMA architectures either since it was a single die. ThreadRipper and Epyc 1 would have been considered NUMA architectures though. NUMA only covers access to main memory. Zen 2 will not be a NUMA architecture since the IO die handles all memory access.
They still have variable access to L3 caches though. There is still some penalty for sharing data across CCXs. Intel uses a mesh network between cores and cache slices to allow mostly uniform access to cache. This burns a lot of power to do this at core clock and it is actually higher latency than what you would see within an AMD CCX. This only comes up when you share data across a CCX boundary, like if you have two threads with shared memory running on different CCXs. You have 4 cores / 8 threads within a CCX, so you have plenty of resources for most things. If you do need to share data across CCXs, then it can still be done efficiently by doing it in a more coarse grained manner. This requires some software optimization in some cases.
With Zen 1, CCX to CCX traffic had to go through an infinity fabric switch at memory clock. This wasn’t really that much of an issue in the first place, but it should be less of an issue with Zen 2. There is no memory clock on the cpu chiplet, so it wouldn’t make any sense for it to operate at memory clock. It probably operates at core clock, so CCX to CCX communication on the same die will probably be much lower latency and higher bandwidth compared to Zen 1. The chip to chip latency should also be quite low due to the high clock speeds of infinity fabric. The bandwidth is more than double what it was in Zen 1.
The IF clock will probably still be locked to memory frequency, because the communication between the I/O die and the chiplets will be IF. By synchronizing the IF clock to the memory clock they can significantly reduce latency to send data from the cores to the memory controller.
The CCX to CCX communication could run with a different IF clock, but I'm not sure if that would make sense, because they would need multiple IF endpoints on every CCX then (one for CCX to CCX, one for CCX to I/O)
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Korguz - Monday, May 27, 2019 - link
Santoval. considering zen 2 looks to be on par, or slightly faster then intel at the clocks they are at... why would they need to be higher ? do you want amd to make intel look worse ? :-)notashill
" And the base is 300Mhz higher which I absolutely believe would increase power draw by 50%, it is simply going way past the efficiency sweet spot of the chip. Very much in line with my experience overclocking the current Ryzen chips. " oh?? 300 mhz = 50% more power ??? would you have a source for this ? also.. Zen 2, is not current ryzen chips.. untill Zen 2 is released, and are reviewed, and in the hands of the public, how Zen 2 overclocks.. is still a mystery...
notashill - Monday, May 27, 2019 - link
Just from my own testing on a 1700, 3.7Ghz all core is about 100W and 4.0 is about 150 and pushing the safe voltage limits. IIRC anandtech's various Ryzen reviews had some good power measurements with overclocking data.Of course 7nm may result in wildly different voltage/power/freq scaling so who knows until the new chips are in the wild to test.
just4U - Monday, May 27, 2019 - link
Linus Tech Tips has a pretty interesting take on all this via their youtube video that's trending up with nearly a million views and 6000 comments in the last 12 hours. I don't doubt for a moment that Ian here has a lot to say about all this stuff as well. Look forward to hearing his thoughts. You guys must be just swamped at Anand over all this. Hopefully pumped to. I have not seen this sort of buzz in quite some time.WaltC - Monday, May 27, 2019 - link
Oh, AMD is saving several eye-openers to be announced in the coming weeks--or my name isn't WaltC...;)just4U - Monday, May 27, 2019 - link
Not sure what else they could drop that wouldn't be underwhelming in comparison to what was released over the last 24hrs. Biggest news day for Amd in over a decade.audi100quattro - Monday, May 27, 2019 - link
Is it real AVX256 now? Also what is the max DDR4 speed for two (16GB) modules per channel?audi100quattro - Monday, May 27, 2019 - link
Also, is the new Ryzen 9 technically NUMA? What are the NUMA trade-offs AMD has made here?jamescox - Tuesday, May 28, 2019 - link
It isn’t NUMA. The original Ryzen processors were not NUMA architectures either since it was a single die. ThreadRipper and Epyc 1 would have been considered NUMA architectures though. NUMA only covers access to main memory. Zen 2 will not be a NUMA architecture since the IO die handles all memory access.They still have variable access to L3 caches though. There is still some penalty for sharing data across CCXs. Intel uses a mesh network between cores and cache slices to allow mostly uniform access to cache. This burns a lot of power to do this at core clock and it is actually higher latency than what you would see within an AMD CCX. This only comes up when you share data across a CCX boundary, like if you have two threads with shared memory running on different CCXs. You have 4 cores / 8 threads within a CCX, so you have plenty of resources for most things. If you do need to share data across CCXs, then it can still be done efficiently by doing it in a more coarse grained manner. This requires some software optimization in some cases.
With Zen 1, CCX to CCX traffic had to go through an infinity fabric switch at memory clock. This wasn’t really that much of an issue in the first place, but it should be less of an issue with Zen 2. There is no memory clock on the cpu chiplet, so it wouldn’t make any sense for it to operate at memory clock. It probably operates at core clock, so CCX to CCX communication on the same die will probably be much lower latency and higher bandwidth compared to Zen 1. The chip to chip latency should also be quite low due to the high clock speeds of infinity fabric. The bandwidth is more than double what it was in Zen 1.
AlexDaum - Saturday, June 1, 2019 - link
The IF clock will probably still be locked to memory frequency, because the communication between the I/O die and the chiplets will be IF. By synchronizing the IF clock to the memory clock they can significantly reduce latency to send data from the cores to the memory controller.The CCX to CCX communication could run with a different IF clock, but I'm not sure if that would make sense, because they would need multiple IF endpoints on every CCX then (one for CCX to CCX, one for CCX to I/O)
formulaLS - Tuesday, May 28, 2019 - link
Yes, it now has full-speed AVX 256 and the supported 3200 Mhz memory speed is 1 Dimm per channel.